Field Plate-Adaptive Doping: A Novel Surface Electric Field Optimization Technique for SOI LDMOS With Gate Field Plate

Huang, Chen-Yang; Guo, Yufeng; Zhang, Jun; Yao, Jiafei; Zhang, Maolin; Du, Lifei; Liu, Jianhua; Tang, W.H.

doi:10.1109/ted.2021.3130837

Cited by 3 publications

(1 citation statement)

References 17 publications

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“…Silicon on insulator (SOI) lateral double-diffused metal oxide semiconductor (LDMOS) typically operates in harsh environments with high voltage. Conventionally, to increase the breakdown voltage (BV) of SOI LDMOS, various techniques have been proposed [1][2][3][4][5][6]. Among these techniques, the field plate (FP) technology has gained widespread popularity due to its simplified fabrication process and superior capability in improving performance.…”

Section: Introductionmentioning

confidence: 99%

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

Chen,

Xia,

You

et al. 2024

IET Power Electronics

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Field plate (FP) technology has been widely used due to its simple structure and process compatibility. Through introducing the interface charge to suppress the electric field peak at the junction region, the breakdown performance can be improved. However, designing an appropriate FP for semiconductor power devices is challenging and time‐consuming. In this paper, the authors propose a fully automated FP optimal design method based on simulated annealing algorithm (SA) for silicon on insulator lateral double‐diffused metal oxide semiconductor. By using an automatic iterative process to obtain the minimum value of the objective function, the parameters related to the FP can be effectively provided. Numerical results show that when the breakdown occurs at the N+N or PN junction, the breakdown voltage can be optimized by an average of 18.6% and 45.5%, respectively. Moreover, compared with the existing methods, the proposed approach is highly efficient with a runtime that does not exceed 12 s. The authors believe that this method can greatly accelerate the power device design process.

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