Field configurable system-on-chip device architecture

Knapp, S.; Tavana, Danesh

doi:10.1109/cicc.2000.852639

Cited by 18 publications

(4 citation statements)

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“…However, they either use a large and extensive RISC core, like the Power PC 440 in Xilinx' Virtex-5 FXT devices [7], or a small microcontroller, like the 8032 8-bit processor in the (discontinued) Triscend E5 chips [8]. None of these devices use a processor specifically optimized for accelerating irregular code.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores

Schüler¹,

Vorbach²,

May³

et al. 2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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This paper describes PACT XPP Technologies' Function-PAE (FNC-PAE) Processor Core which was designed for executing irregular, control-flow dominated code efficiently in embedded systems. It combines aspects of dynamically reconfigurable coarse-grain arrays and VLIW processors. The siliconproven FNC-PAE Cores are tightly integrated with the XPP reconfigurable dataflow array. We present the FNC-PAE architecture, its development environment (assembler, C compiler, and simulator), application examples, and performance data collected from the fully working prototype chip.

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Section: Related Workmentioning

confidence: 99%

Dynamic Reconfiguration for Irregular Code Using FNC-PAE Processor Cores

Schüler¹,

Vorbach²,

May³

et al. 2011

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PHD Forum

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“…Steve Knapp from Triscend Corporation [41] (now acquired by Xilinx [42]) described a configurable system bus called a Configurable System Interconnect (CSI) Bus for a CSoC architecture which was an emerging idea around 2000 [43]. The CSI Bus was specifically designed to facilitate re-use, timing reliability, increment in overall throughput, and reduction in debug time in applications that demanded short TTM as well as field adaptability.…”

Section: Becker Et Al Described Different Heterogeneous Soc Architecmentioning

confidence: 99%

“…A Configurable System on Chip (CSoC) can be designed on a single chip such as in a modern FPGA consisting of thousands of logic blocks and a diverse set of on-chip resources such as distributed memory, DSP blocks etc. Such heterogeneous platforms, often called CSoC in existing literature [43] [44], are becoming increasingly popular, aptly driven by fast development of VLSI technologies to enable such on-chip integration [17], [37], [72]. While these architectures provide obvious advantages in terms of cost and flexibility of implementation, such complex system design introduces a set of challenges for industrial designers and academics.…”

Section: Configurable System On Chip (Csoc)mentioning

confidence: 99%

Constraint-aware configurable system-on-chip design for embedded computing

Prakash¹

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Field Programmable Gate Arrays (FPGAs) are rapidly becoming a popular alternative to ASICs as they continue to increase in capacity, functionality and performance. At the same time, FPGA developers are faced with the challenges of meeting increasingly aggressive design constraints such as power, delay and area costs without violating shorter Time-to-Market (TTM) pressures and lower Non-Recurring Engineering (NRE) costs for embedded systems development. In this research, efficient techniques have been proposed for processor subsetting and customization as well as the rapid generation of application-specific hardware accelerators in order to meet the design constraints of configurable System-on-Chip (SoC) platforms. A processor-agnostic technique has been devised for sub-setting soft-core processors by relying on LLVM compiler generated front-end application output. The proposed approach has resulted in a systematic method for the application-aware sub-setting of the micro-architecture subsystems such as hardware multipliers and floating point units of a soft-core processor. Evaluations based on widely used benchmarks show that the proposed method can be deployed to reliably subset soft core processors at high-speed without compromising compute performance. A technique for the architecture-aware enumeration of custom instructions has been proposed next to identify area-efficient custom instructions by employing FPGA resource-aware pruning of the search space. Experimental results based on applications from widely-used benchmark suites confirm that deploying custom instructions identified in this way can improve compute performance by up to 65%. The instruction level parallelism (ILP) has also been exploited to further improve the compute performance by identifying profitable coarsegrained custom instructions. It has been demonstrated that the custom instructions using the proposed method can accelerate computations by up to 39% when compared to a base processor only implementation. Unlike traditional custom instruction generation methods that are incapable of incorporating memory-dependent basic blocks, a novel technique for accelerating memory-dependent basic blocks has been proposed. A detailed data dependency analysis based on pre-defined memory allocation in an application has been developed to guarantee the identification of ix profitable basic blocks for hardware acceleration. The profitability of a code segment for hardware acceleration is determined by using a mathematical model to represent the overheads associated with the placement of data in both the local and main memory subsystems. The proposed approach for hardware acceleration eliminates the need for Direct Memory Access (DMA) transfers or cache-coherence protocols. A scalable technique for the automatic selection of profitable basic blocks for hardware acceleration has been devised in order to overcome the time complexity of the search space. It relies on a heuristic approach to significantly reduce the search space, thereby resulting in a high-spe...

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“…As the design moves to systemlevel integration, the control logic and the computationallyintensive logic are usually separated. Configurable Systemon-Chip (CSoC) devices [3,11], which are a combination of embedded microprocessors, memory and embedded programmable logic, have attracted academic research and also resulted in industrial products such as Triscend A7, Xilinx VirtexII Pro and Altera Excalibur. Each of them has one or more embedded microprocessors using different instruction set architectures at different clock speeds, and large programmable logic resources.…”

Section: Introductionmentioning

confidence: 99%