Reconfigurable Elliptic Curve Cryptosystems on a Chip

Abstract

This paper presents a System-on-a-Chip (SoC)

Hardware/Software Co-Design Implementations of Elliptic Curve Cryptosystems

“…Despite that normal basis representation provides more efficient hardware, Table 1 shows that the implementations that use polynomial basis (Janssens et al, 2001;Ernst et al, 2002;Koschuch et al, 2006;Batina et. al., 2006) are more than implementations that use normal basis (Zeng et al, 2002;Cheung et al, 2005;Ramsey, 2008). The partitioning schemes, on the other hand, starts by a pure software implementation scheme (Ernst et al, 2002;Cheung et al, 2005).…”

“…al., 2006) are more than implementations that use normal basis (Zeng et al, 2002;Cheung et al, 2005;Ramsey, 2008). The partitioning schemes, on the other hand, starts by a pure software implementation scheme (Ernst et al, 2002;Cheung et al, 2005). Then, the partitioning schemes differ in which part of the ECC remains on software and which is implemented by hardware.…”

“…Table 1 summarizes the underlying finite field, the representation basis, and the number of bits of these implementations. Clearly, Table 1 shows that all the implementations use binary fields GF(2 m ) and none of these implementations use prime fields GF(p) (Janssens et al, 2001;Zeng et al, 2002;Ernst et al, 2002;Cheung et al, 2005;Koschuch et al, 2006;Batina et. al., 2006;Ramsey, 2008).…”

“…The four partitioning schemes presented in (Cheung et al, 2005) include: a pure software implementation scheme, a scheme that uses a hardware multiplier, a scheme that uses a hardware inverter and a scheme that implements point multiplication in hardware. The four proposed partitioning schemes were implemented on the Xilinx ML310 board containing a XC2VP30 FPGA chip with m = 113, 162, 270 bits using normal basis.…”

Designing a Posture Analysis System with Hardware Implementation

“…FPGAs (Field-programmable Gate Arrays) provide an attractive alternative: they combine the flexibility of software with a speed approaching that of custom hardware technology. It has been shown that, for selected applications, an FPGA at tens of MHz can run up to 1,000 times faster than a microprocessor with a GHz clock [5,16], while moving critical software loops into hardware can result in average energy savings of 35 to 70% with an average speedup of 3-7 times, depending on the particular device used [19].…”