FFT coefficient memory reduction technique for OFDM applications

Hasan, M. Arif; Arslan,

doi:10.1109/icassp.2002.1005933

Cited by 3 publications

(2 citation statements)

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“…As with the Radix-4, Burst I/O architecture, data can be simultaneously loaded and unloaded when the output samples are in bit reversed order. This solution supports point sizes from 8 …”

Section: Radix-2 Burst I/o Architecturesupporting

confidence: 74%

Simulation and Analysis of DIT FFT Algorithm for Spartan 3 FPGA

Verma¹,

Sindal²

2013

2013 International Conference on Communication Systems and Network Technologies

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The Fast Fourier Transform (FFT) and its Inverse (IFFT) is one of the most widely used algorithms in digital signal processing. Using this transform, signals can be moved to the frequency domain where filtering and correlation can be performed with fewer operations. The Fast Fourier Transform (FFT) algorithm reduces the computation time of the Fourier transform by orders of magnitude. This permits the implementation of increasingly sophisticated signal processing algorithms with processing times that allowed interaction with the system. FFT is a fundamental building block used in DSP system. It has been widely applied in the analysis and implementation of digital communication systems, with application ranging from OFDM based digital modems, software defined radio, phase correlation system.

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“…As with the Radix-4, Burst I/O architecture, data can be simultaneously loaded and unloaded when the output samples are in bit reversed order. This solution supports point sizes from 8 …”

Section: Radix-2 Burst I/o Architecturesupporting

confidence: 74%

Simulation and Analysis of DIT FFT Algorithm for Spartan 3 FPGA

Verma¹,

Sindal²

2013

2013 International Conference on Communication Systems and Network Technologies

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“…However, these factors can be computed from N /8 + 1 complex-valued numbers with the aid of an add/subtract unit [17]. On the other hand, there are N /4 + 1 different real-valued magnitudes present in the real and imaginary parts, thus the twiddle factors can be formed easily by fetching the magnitudes from a table and taking complement when needed.…”

Section: Operand and Twiddle Factor Storagementioning

confidence: 99%

Scalable FFT Processors and Pipelined Butterfly Units

Takala

Punkka

2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper considers partial-column radix-2 FFT processors and realizations of butterfly operations. The area and power-efficiency of butterfly units to be used in the proposed processor organization based on bitparallel multipliers, distributed arithmetic, and CORDIC are analyzed and compared. All the selected butterfly units are synthesized onto the same 0.11 μ ASIC technology allowing the results to be compared. The proposed processor organization permits the area of the FFT implementation to be traded against the computation time, thus the final structure can be easily tailored according to the requirements of the given application. The power consumption comparison shows that butterflies based on bit-parallel multipliers are power-efficient but have limitations on clock frequency. Butterflies based on distributed arithmetic could be used when higher clock frequencies are used. If extremely long FFTs are needed, the CORDIC based butterflies are applicable.

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Scalable FFT Processors and Pipelined Butterfly Units

Takala

Punkka

2004

Lecture Notes in Computer Science

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FFT coefficient memory reduction technique for OFDM applications

Cited by 3 publications

References 0 publications

Simulation and Analysis of DIT FFT Algorithm for Spartan 3 FPGA

Simulation and Analysis of DIT FFT Algorithm for Spartan 3 FPGA

Scalable FFT Processors and Pipelined Butterfly Units

Scalable FFT Processors and Pipelined Butterfly Units

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