Fetch halting on critical load misses~~~~~~~~

Mehta, Neha; Singer, Bernhard; Bahar, R. Iris; Leuchtenburg, M.; Weiss, Richard

doi:10.1109/iccd.2004.1347929

Cited by 9 publications

(3 citation statements)

References 26 publications

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“…Selective throttling [2] focuses on reducing energy dissipated by wrong-path instructions and dynamically chooses the optimal throttling technique applied to each branch depending on the branch prediction confidence level. Fetch halting [14] stops fetching instructions when long-latency critical load misses occur to reduce early-fetched instructions. In [3,6,9,15,16], the resources of superscalar processors, such as issue queue, reorder buffer, and load/store queue, are dynamically re-sized according to program needs to reduce the energy consumed by these resources.…”

Section: Related Workmentioning

confidence: 99%

Adaptive front-end throttling for superscalar processors

Zhang

Lach

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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To achieve high performance, conventional superscalar processors maintain maximum front-end instruction delivery bandwidth, which is often suboptimal when program behavior and priority metrics change. This paper proposes an adaptive front-end throttling technique that dynamically adjusts the front-end instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. Circuit-level synthesis (45nm FreePDK) and simulation show that adaptive front-end throttling incurs negligible overhead but achieves average improvements of 7%, 28%, 28%, and 32% for performance, energy, energy-delay product, and energy-delay-squared product, respectively, over all benchmarks on an 8-way superscalar processor.

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Section: Related Workmentioning

confidence: 99%

Adaptive front-end throttling for superscalar processors

Zhang

Lach

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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“…Prior works [8,9,14,23,26,36,49,50,54,57] have proposed various energy-saving techniques that dynamically allocate datapath resources according to the needs of applications. These energysaving techniques suffer from two problems.…”

Section: Dynamic Core Scalingmentioning

confidence: 99%

“…Selective throttling [6] focuses on reducing energy dissipated by wrong-path instructions and dynamically chooses the optimal throttling technique applied to each branch depending on the branch prediction confidence level. Fetch halting [50] stops fetching instructions when long-latency critical load misses occur to reduce early-fetched instructions.…”

Section: Front-end Throttlingmentioning

confidence: 99%

Scrutinizing Resource Utilization for High Performance and Low Energy Computation

Zhang

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Modern processors often suffer from inefficient resource utilization, which leads to inferior performance and energy efficiency. This dissertation scrutinizes the utilization of datapath and cache resources in superscalar processors for opportunities to improve performance and energy efficiency.Traditional superscalar processors usually employ a one-size-fits-all design approach that allocates a fixed amount of resources for all applications at all times to deliver the best overall performance. However, the one-size-fits-all approach is not always energy efficient, because both the application behavior and the use scenario are changing all the time and the demand for processor resources is also changing accordingly.To improve the utilization of datapath resources, this dissertation proposes an adaptive processor that dynamically allocates datapath resources based on the needs of applications and use scenarios. The adaptive processor is applied to two use cases to improve energy efficiency. In the first use case (front-end throttling (FET)), the adaptive processor dynamically throttles the frontend instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. In the second use case (dynamic core scaling (DCS)), the adaptive processor extends performance-energy tradeoff capabilities in superscalar processors by scaling datapath resource rather than voltage. The adaptive processor ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS significantly extends the range of performance-energy tradeoffs.Caches also suffer from inefficient utilization in modern processors. To minimize the access iv v latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup.However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. To improve the utilization of the L1 instruction cache, this dissertation proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that only the matching data way need to be accessed. ETL incurs no performance penalty and insignificant hardware overhead, but dramatically reduces the read energy of L1 instruction cache.For memory intensive workloads, caches often suffer from thrashing, i.e., high-reuse blocks evicting each other from the cache due to the lack of space. To reduce thrashing, only a fraction of the working set should be kept in the cache, so that at least this fraction stays longer in the cache to enable reuse before eviction. However, prior insertion policies take an ad hoc approach to selecting that fraction, e.g., inserting blocks with high priority at ...

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