Ferroelectric ternary content-addressable memory for one-shot learning

Ni, Kai; Yin, Xunzhao; Laguna, Ann Franchesca; Joshi, Siddharth; Dünkel, Stefan; Trentzsch, Martin; Müller, Johannes; Beyer, Sven; Niemier, Michael; Hu, Xiaobo Sharon; Datta, Suman

doi:10.1038/s41928-019-0321-3

Cited by 252 publications

(213 citation statements)

References 40 publications

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“…Even with thermal-aware training using (14) the target phases and thus the temperatures of some MZIs may still dier much instead of being balanced. Consequently, MZIs with dierent temperatures aect each other and cause their phases to deviate from the expected values.…”

Section: Power Adjustment To Counter Thermal-eected Inaccuracymentioning

confidence: 99%

“…We then generate a given number of samples according to noise distributions and inject them into the phases. The gradients with the cost function in (14) are updated with respect to all these random samples and stored for online tuning later.…”

Section: Characterized Tuning Of Onnsmentioning

confidence: 99%

“…Deep neural networks have achieved remarkable breakthroughs in various classication tasks in recent years. To accelerate the operations in such networks, various hardware platforms with emerging devices, e.g, RRAM/memristor [1][2][3][4][5][6], optical device [7][8][9], spintronics device [10,11] and Ferroelectric Field-Eect Transistor [12][13][14][15] have been proposed. One such promising platform is optical neural networks (ONNs).…”

Section: Introductionmentioning

confidence: 99%

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Countering variations and thermal effects for accurate optical neural networks

Zhu

Zhang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Power Adjustment To Counter Thermal-eected Inaccuracymentioning

confidence: 99%

Section: Characterized Tuning Of Onnsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Countering variations and thermal effects for accurate optical neural networks

Zhu

Zhang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…In the machine learning era, memory-augmented neural networks (MANNs) are quickly emerging to tackle the challenges of traditional DNNs in areas such as one-shot learning [64], [65]. MANNs rely on differentiable external memory to decouple the dynamic state from the neural network.…”

Section: Non-mesh-based Interconnectsmentioning

confidence: 99%

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Nabavinejad

Baharloo

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand

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“…Recent work developing CAMs changing the underlying technology from SRAM to emerging nonvolatile device technologies has shown promise in addressing the historical CAM design challenges of area, power, speed, and search margin [17] -thus motivating CAM usage as an in-memory compute primitive for a wider diverse range of computational models (see Figure 1). With the promise of lower power and cost with new CAM designs, researchers have explored their usage in finite state machines, [18] machine learning and data mining, [19,20] tree-based models, and arbitrary logic functions [14,17] in addition to the associative and reconfigurable computing models noted above. The shift to emerging device technologies in CAM circuits has also provided additional design flexibility with new circuit structures for smaller circuits and furthering in-memory compute capabilities leveraging analog capabilities as well.…”

mentioning

confidence: 99%

In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching

Graves

Sheng

et al. 2020

Advanced Materials

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The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in‐memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.

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Ferroelectric ternary content-addressable memory for one-shot learning

Cited by 252 publications

References 40 publications

Countering variations and thermal effects for accurate optical neural networks

Countering variations and thermal effects for accurate optical neural networks

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching

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