Ferroelectric Gate Field-Effect Transistors with 10nm Thick Nondoped HfO&lt;sub&gt;2&lt;/sub&gt; Utilizing Pt Gate Electrodes

IEEE J. Electron Devices Soc.

Ohtaguchi

Ihara

et al. 2021

We have investigated the ferroelectric hafnium nitride (HfN) thin films directly formed on the Si(100) substrate for the metal-ferroelectrics-Si field-effect transistor (MFSFET) applications. The 10 nm thick rhombohedral phase HfN layer was found to be formed on the Si(100) substrate utilizing the postmetallization annealing (PMA) at 400 o C/5 min for HfN0.5/HfN1.15/Si(100) MFS diode structure which was deposited with in situ process by the electron cyclotron resonance (ECR) plasma reactive sputtering. The remnant polarization (2Pr) of 24.0 C/cm 2 with the coercive field (Ec) of 3.8 MV/cm was obtained from the P-V characteristic under the voltage sweep of ±𝟏𝟎 V. Fatigue characteristics without wake-up were confirmed until 10 9 program/erase (P/E) cycles under the input pulses of ±𝟔 V/5 s although the 2Pr was gradually decreased to 10.7 C/cm 2 . The polarization (Psw) of 13.4 C/cm 2 was clearly observed by the positive-up negative-down (PUND) measurements utilizing the input pulses of ±𝟔 V/5 s. The memory window (MW) of 0.32 V was realized in the C-V characteristics by the program operation at -10 V/1 s.

“…where q is elementary charge and N is sheet carrier density. Therefore, the obtained polarization values of the ferroelectric HfNx are enough for the MFSFET application [17]. Fig.…”

Section: Resultsmentioning

confidence: 81%

Section: Resultsmentioning

confidence: 95%

See 1 more Smart Citation

Ferroelectric Hafnium Nitride Thin Films Directly Formed on Si(100) Substrate

IEEE J. Electron Devices Soc.

Ohtaguchi

Ihara

et al. 2021

“…Figure 1 shows the experimental procedure for the MFS diodes and n-channel MFSFET with 5 nm-thick ferroelectric nondoped HfO 2 gate insulator utilizing conventional gate-last process [15], [16]. The schematic cross-sections and the plane-views of the fabricated MFS diodes and MFS-FET are also shown.…”

Section: Methodsmentioning

confidence: 99%

Kr-Plasma Sputtering for Pt Gate Electrode Deposition on MFSFET with 5 nm-Thick Ferroelectric Nondoped HfO<sub>2</sub> Gate Insulator for Analog Memory Application

Shin

Tanuma

2023

IEICE Trans. Electron.

Self Cite

In this research, we investigated the threshold voltage (V TH ) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO 2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2P r ) of 7.2 µC/cm 2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of −5/5 V, 100 ms. Furthermore, the V TH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

“…Figure 1 shows the experimental procedures of the MFS diodes and the n-channel MFSFET with 5 nm thick ferroelectric nondoped HfO 2 gate insulator utilizing conventional gate-last process. 27) The schematic cross-sections and the plane-views of the fabricated MFS diodes and MFSFET are also shown. For the fabrication of MFS diodes, lightly doped p-Si(100) (10-30 Ωcm) and heavily doped p + -Si(100) (0.01-0.05 Ωcm) substrates were cleaned by sulfuric-peroxide mixture and diluted HF (DHF) solutions.…”

Section: Experimental Methodsmentioning

confidence: 99%

Effects of sputtering power on the formation of 5 nm thick ferroelectric nondoped HfO₂ gate insulator for MFSFET application

Shin

Tanuma

2022

Jpn. J. Appl. Phys.

Self Cite

In this research, the effects of sputtering power on the ferroelectric property of 5 nm thick ferroelectric nondoped HfO2 were investigated for metal-ferroelectric-semiconductor field-effect-transistor (MFSFET) application. The remnant polarization (2Pr) was increased to 5.9 μC/cm2, and the density of interface states (Dit) at silicon interface was effectively reduced to 1.8×1011 cm-2 eV-1 when the sputtering power was 50 W for 5 nm thick nondoped HfO2 formation. The largest Weibull slope (β) of 1.76 was extracted in Weibull distribution plot of the time dependent dielectric breakdown (TDDB) measurements, and excellent fatigue properties until 1010 cycles were realized. The memory window (MW) of 0.56 V was realized by the pulse amplitude and width of -1/6 V and 100 ms, respectively. Furthermore, the memory characteristic was expected to be maintained ever after 10 years of retention time.