FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

Anderson, J.; Bauer, K. T.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Miotto, G. Lehmann; Levinson, L. J.; Narevicius, Julia; Vazquez, J. G. Panduro; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, Jörn; Vandelli, W.; Vermeulen, J. C.; Whiteson, D.; Wu, W.; Zhang, J.

doi:10.1088/1748-0221/11/12/c12023

Cited by 52 publications

(40 citation statements)

References 11 publications

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“…It is based on a Xilinx Kintex UltraScale FPGA (XCKU115-FLVF-1924) capable of supporting 48 bi-directional high-speed optical links via on-board MiniPOD transceivers, with a 16-lane PCIe Gen3 interface. In comparison to the previous version (FLX-711), the FLX-712 no longer hosts the unneeded DDR4 SODIMM connectors [7]. This eases PCB routing and also makes the board shorter.…”

Section: The Felix Interface Cardmentioning

confidence: 99%

FELIX: the New Detector Interface for the ATLAS Experiment

2019

IEEE Trans. Nucl. Sci.

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During the next major shutdown (2019)(2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunchcrossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGAbased PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event fragment building and buffering, with support for detector or trigger specific data processing, and will serve the data upon request to the ATLAS High Level Trigger for Event Building and Selection. This paper will cover the design and status of FELIX, the SW ROD, results of early performance testing and integration tests with several ATLAS front-ends.

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Section: The Felix Interface Cardmentioning

confidence: 99%

FELIX: the New Detector Interface for the ATLAS Experiment

2019

IEEE Trans. Nucl. Sci.

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“…Figure 2 shows the eye diagram of a 1-hour test for a high-speed communication that we have carried out to validate the GBT protocol over the SFP connector. These tests are performed also to integrate our work within the ATLAS TDAQ collaboration and in particular with the FELIX group, so to interface with electronic boards called FELIX [8][9]. Eventually the…”

Section: Testsmentioning

confidence: 99%

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

Gabrielli¹,

Alfonsi²,

D’amen³

et al. 2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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“…For this multi-channel 1Definition of the boundary between TX and RX may be different with Figure 3. project, the limit of the clock resources in FPGA should be considered. The FPGA on the FELIX prototype is Kintex Ultrascale [6] which has more than 1000 global buffers, so each GBT channel can use independent clocks. While for the Virtex-7 FPGA on the FELIX demonstrator, the number of global buffers is 32, so the clocks must be shared between different channels.…”

Section: Clock Sharing In the Multichannel Designmentioning

confidence: 99%

Optimization on fixed low latency implementation of the GBT core in FPGA

Chen

et al. 2017

J. Inst.

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A: In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end [3], correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [4]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [5, 6] is used to interface the frontend electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper. K: Fixed low latency transmission; GBT link; Transceiver in FPGA arXiv:1608.08916v4 [physics.ins-det]

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FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

Cited by 52 publications

References 11 publications

FELIX: the New Detector Interface for the ATLAS Experiment

FELIX: the New Detector Interface for the ATLAS Experiment

A Multi-Channel PCI Express Readout Board Proposal for the Pixel Upgrade at LHC

Optimization on fixed low latency implementation of the GBT core in FPGA

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