FeFET: A versatile CMOS compatible device with game-changing potential

Beyer, Sven; Dünkel, Stefan; Trentzsch, Martin; Müller, Johannes; Hellmich, A.; Utess, Dirk; Paul, J.; Kleimaier, Dominik; Pellerin, John; Müller, Stefan; Ocker, J.; Benoist, Antoine; Zhou, Haidi; Mennenga, Menno; Schuster, Martin; Fabio, Tassan; Noack, Marko; Pourkeramati, A.; Müller, F.; Lederer, Maximilian; Ali, Tarek; Hoffmann, R.; Kämpfe, Thomas; Seidel, Konrad; Mulaosmanovic, Halid; Breyer, Evelyn T.; Mikolajick, Thomas; Slesazeck, Stefan

doi:10.1109/imw48823.2020.9108150

Cited by 100 publications

(53 citation statements)

References 10 publications

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“…It is well known that FeFETs processed on the same wafer are affected by device-to-device variation due to the grain distribution in the ferroelectric thin film [16], [24]- [26]. Each time different PG/ER pulse schemes were used to provide statistically reliable data, up to 20 devices were measured for each extraction of VT and SS.…”

Section: Resultsmentioning

confidence: 99%

“…Since the size of the memory window (MW), which is the threshold voltage (VT) difference between program (PG) state and erase (ER) state, is one of the most important performance factors of the memory device, the evolution of the MW by PG/ER cycling has been extensively investigated [12]- [16]. At the initial stage of PG/ER cycling, the MW increases due to the wake-up effect of ferroelectric thin film.…”

Section: Introductionmentioning

confidence: 99%

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Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Min

Ronchi

McMitchell

et al. 2021

IEEE Electron Device Lett.

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The endurance of the HfO2-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (Tramp), which is the time to reach the PG/ER voltage, and the hold time (Thold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10 4 by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long Tramp but short Thold are desirable to suppress the interface trap generation in FeFET. The relation between Tramp, Thold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Min

Ronchi

McMitchell

et al. 2021

IEEE Electron Device Lett.

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“…Thus, the deposition of this ferroelectric material in thin controlled layers with state-of-the-art techniques and in diverse struc- tures, intermixed layers, nanolaminates and 3D structures has been accomplished due to the widespread experience and facile growth techniques available for HfO 2 and ZrO 2 . Along with these advantages, different device concepts have been successfully demonstrated spanning from ferroelectric field effect transistors (FeFETs) 5 to ferroelectric non-volatile random access memories (FeRAMs) 6 to ferroelectric tunnel junctions (FTJs). 7 In the last years, neuromorphic applications were also widely addressed.…”

Section: Introductionmentioning

confidence: 99%

Interplay between oxygen defects and dopants: effect on structure and performance of HfO₂-based ferroelectrics

Materano

Lomenzo

Kersch

et al. 2021

Inorg. Chem. Front.

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“…The discovery of ferroelectricity in the fluorite structure-based hafnium oxide materials [7,8] marked a change in FeFET technology development. It was promoted as an ideal low-cost embedded memory solution [9]. On a system level, the FeFET offers several merits as a low power operation: a fast-switching speed and a short access time.…”

Section: Introductionmentioning

confidence: 99%

Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

Ali

Kühnel

Olivo

et al. 2021

Electronic Materials

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A multi-level cell (MLC) operation as a 1–3 bit/cell of the FeFET emerging memory is reported by utilizing optimized Si doped hafnium oxide (HSO) and hafnium zirconium oxide (HZO) based on ferroelectric laminates. An alumina interlayer was used to achieve the thickness independent of the HSO and HZO-based stack with optimal ferroelectric properties. Various split thicknesses of the HSO and HZO were explored with lamination to increase the FeFET maximum memory window (MW) for a practical MLC operation. A higher MW occurred as the ferroelectric stack thickness increased with lamination. The maximum MW (3.5 V) was obtained for the HZO-based laminate; the FeFETs demonstrated a switching speed (300 ns), 10 years MLC retention, and 104 MLC endurance. The transition from instant switching to increased MLC levels was realized by ferroelectric lamination. This indicated an increased film granularity and a reduced variability through the interruption of ferroelectric columnar grains. The 2–3 bit/cell MLC levels and maximum MW were studied in terms of the size-dependent variability to indicate the impact of the ferroelectric area scaling. The impact of an alumina interlayer on the ferroelectric phase is outlined for HSO in comparison to the HZO material. For the same ferroelectric stack thickness with lamination, a lower maximum MW, and a pronounced wakeup effect was observed in HSO laminate compared to the HZO laminate. Both wakeup effect and charge trapping were studied in the context of an MLC operation. The merits of ferroelectric stack lamination are considered for an optimal FeFET-based synaptic device operation. The impact of the pulsing scheme was studied to modulate the FeFET current to mimic the synaptic weight update in long-term synaptic potentiation/depression.

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FeFET: A versatile CMOS compatible device with game-changing potential

Cited by 100 publications

References 10 publications

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Interplay between oxygen defects and dopants: effect on structure and performance of HfO₂-based ferroelectrics

Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

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FeFET: A versatile CMOS compatible device with game-changing potential

Cited by 100 publications

References 10 publications

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor

Interplay between oxygen defects and dopants: effect on structure and performance of HfO2-based ferroelectrics

Impact of the Ferroelectric Stack Lamination in Si Doped Hafnium Oxide (HSO) and Hafnium Zirconium Oxide (HZO) Based FeFETs: Toward High-Density Multi-Level Cell and Synaptic Storage

Contact Info

Product

Resources

About

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Interplay between oxygen defects and dopants: effect on structure and performance of HfO₂-based ferroelectrics