Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework

Abstract

© MASTER SERIES Feature

A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates

“…The current interest in MCML circuits is mainly due to their use in mixedsignal integrated circuits [1,2]. Major advantages of them are low crosstalk due to the low output voltage swing, good noise immunity to supply noise due to their differential nature and low generated supply noise due to supply current almost constant during the output-voltage switching.…”

“…Since their delay is an increasing function of that current [1,2], the faster are the circuits the more energy they consume. Hence, it is crucial to be able to quantify the tradeoff that can be realized between speed and energy in order to design energyefficient MCML circuits.…”

“…That also occurs in designs optimized for speed, when using sub-100 nm technologies. Unfortunately, at the best of the author's knowledge, all the delay models for MCML circuits utilized in the technical literature are based on the assumption that the NMOS transistors of the pull-down network are operating in the strong inversion region [1,2]. So, in order to quantify the energy-delay tradeoff, it is necessary to develop a delay model valid in all the operation regions of the MOS transistor, namely, weak inversion (subthreshold) moderate inversion (near-threshold) and strong inversion.…”

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff

“…In differential logic styles such as MCML, each signal is carried by a pair of wires that switch in opposite directions, thus canceling out the power supply and substrate noise to a large extent [5][6][7][8][9][10][11][12][13]. The maximum benefits are obtained when each differential signal pair is routed as a bundle (usually named ''fully differential pair''), in which the two complementary wires have exactly the same length [3][4][5][6][7]11].…”

“…In addition, wires within the same pair always experience opposite transitions, hence their effective coupling capacitance is always increased by a factor of two due to the Miller effect [2,[11][12][13]. For these reasons, the choice of the wire grid pitch is expected to be a critical design variable in differential design flows, and further investigation is needed.…”