Feasibility study of mask fabrication in double exposure technology

Doh, Jong Gul; Lee, Sangeun; Yoon, Je Bum; Lee, Doo Youl; Cho, Seong‐Yong; Kim, Byung Gook; Choi, Seong Woon; Han, Woo-Jin

doi:10.1117/12.686523

Cited by 2 publications

(3 citation statements)

References 4 publications

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“…Registration and mask CD are at mask (4X) scale; all other dimensions are ay 1X scale. Mask registration error can be lumped into overlay but we track it separately here (J. G. Doh et al 7 discuss mask registration errors in detail). We assume that these quantities are zero-mean random variables: Fig.…”

Section: Variance Of Space-widthsmentioning

confidence: 99%

Double patterning technology: process-window analysis in a many-dimensional space

Sezginer¹,

Yenikaya²,

Staud³

2007

SPIE Proceedings

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We consider a memory device that is printed by double patterning (litho-etch-litho-etch) technology wherein positive images of ¼-pitch lines are printed in each patterning step. We analyze the errors that affect the width of the spaces. We propose a graphical method of visualizing the many-dimensional process-window for double patterning. Controlling the space-width to 10% of half-pitch is not possible under the worst combination of errors. Statistical analysis shows that overlay and etch bias are the most significant contributors to the variability of spaces. 3 [space-width] = 17% and 11% of nominal space can be achieved for 3 [Overlay] = 6 nm and 3 nm, respectively, for a 40-nm half pitch array printed using NA=0.93.

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Section: Variance Of Space-widthsmentioning

confidence: 99%

Double patterning technology: process-window analysis in a many-dimensional space

Sezginer¹,

Yenikaya²,

Staud³

2007

SPIE Proceedings

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“…If the scribe line structures were written in the same run as the chip, this would improve their placement, and the scribe line registration would be more meaningful. The difference in pattern density in the scribe line compared to the die should also be noted 6 . In other words, judging the quality of a reticle by the standard registration measurements in the scribe line is not representative at all of the placement of the structures in the die.…”

Section: Registration Error and Reticle-to-reticle Overlaymentioning

confidence: 99%

“…The individual contributors to the total overlay error budget have been classified and measured or estimated in the past in various studies 3,4 . Besides scanner lenses, stages and alignment mark quality, the impact of reticle registration on the overall overlay budget comes more and more into the focus of the work5, 6 work hard to decrease the registration of the reticle. However, the transfer of the reticle registration onto the wafer has not yet been fully explored on production reticles 7 .…”

Section: Introductionmentioning

confidence: 99%

Meeting overlay requirements for future technology nodes with in-die overlay metrology

Schulz¹,

Seltmann²,

Busch³

et al. 2007

SPIE Proceedings

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As a consequence of the shrinking sizes of the integrated circuit structures, the overlay budget shrinks as well. Overlay is traditionally measured with relatively large test structures which are located in the scribe line of the exposure field, in the four corners. Although the performance of the overlay metrology tools has improved significantly over time it is questionable if this traditional method of overlay control will be sufficient for future technology nodes. For advanced lithography techniques like double exposure or double patterning, in-die overlay is critical and it is important to know how much of the total overlay budget is consumed by in-die components.We reported earlier that small overlay targets were included directly inside die areas and good performance was achieved 1 . This new methodology enables a wide range of investigations. This provides insight into processes which were less important in the past or not accessible for metrology. The present work provides actual data from productive designs, instead of estimates, illustrating the differences between the scribe line and in-die registration and overlay. The influence of the pellicle on pattern placement on mask and wafer overlay is studied. Furthermore the registration overlay error of the reticles is correlated to wafer overlay residuals. The influence of scanner-induced distortions (tool to tool differences) on in-die overlay is shown. Finally, the individual contributors to in-die-overlay are discussed in the context of other overlay contributors. It is proposed to use in-die overlay and registration results to derive guidelines for future overlay and registration specifications. It will be shown that new overlay correction schemes which take advantage of the additional in-die overlay information need to be considered for production.

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Feasibility study of mask fabrication in double exposure technology

Cited by 2 publications

References 4 publications

Double patterning technology: process-window analysis in a many-dimensional space

Double patterning technology: process-window analysis in a many-dimensional space

Meeting overlay requirements for future technology nodes with in-die overlay metrology

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