FDSOI: From substrate to devices and circuit applications

Mazuré, C.; Ferrant, R.; Nguyen, Bich‐Yen; Schwarzenbach, W.; Moulin, C.

doi:10.1109/esscirc.2010.5619767

Cited by 13 publications

(8 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For siliconon-insulator (SOI) devices, variations of the thicknesses of the silicon layer contribute to the statistical variations. For advanced SOI substrates, this variation across the wafer is less than 1 nm, and empirically, an impact of about 25 mV/nm was found [6]. Own studies for fully depleted (FD) SOI transistors based on ITRS specifications for silicon film thickness variations led to similar figures [7].…”

Section: Sources Of Process Variationsmentioning

confidence: 55%

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology.

show abstract

Section: Sources Of Process Variationsmentioning

confidence: 55%

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…This section analyzes the implementation of the proposed DMA engine in STMicroelectronics 28 nm UTB FD-SOI technology [17]. The results reported in this section, refers to the postsynthesis implementation of the DMA, as well as all the cluster, performed with Synopsys design compiler configured in topographical mode.…”

Section: Implementation Resultsmentioning

confidence: 99%

Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters

Rossi

Loi

Haugou

et al. 2014

Proceedings of the 11th ACM Conference on Computing Frontiers

View full text Add to dashboard Cite

The evolution of multi-and many-core platforms is rapidly increasing the available on-chip computational capabilities of embedded computing devices, while memory access is dominated by on-chip and off-chip interconnect delays which do not scale well. For this reason, the bottleneck of many applications is rapidly moving from computation to communication. More precisely, performance is often bound by the huge latency of direct memory accesses. In this scenario the challenge is to provide embedded multi and many-core systems with a powerful, low-latency, energy efficient and flexible way to move data through the memory hierarchy level. In this paper, a DMA engine optimized for clustered tightly coupled many-core systems is presented. The IP features a simple micro-coded programming interface and lock-free per-core command queues to improve flexibility while reducing the programming latency. Moreover it dramatically reduces the area and improves the energy efficiency with respect to conventional DMAs exploiting the cluster shared memory as local repository for data buffers. The proposed DMA engine improves the access and programming latency by one order of magnitude, it reduces IP area by 4x and power by 5x, with respect to a conventional DMA, while providing full bandwidth to 16 independent logical channels.

show abstract

“…Thus, the contribution of each element in terms of memory performance degradation is demonstrated. A 28-nm Fully Depleted Silicon-On-Insulator (FDSOI) technology is considered for simulations [13]. Memory array cells are first placed in a virgin state.…”

Section: Simulation Resultsmentioning

confidence: 99%