Fault tolerant VLSI systems

Abstract

This paper examines the wide variety of fault tolerance techniques applied to VLSl technology. We provide a brief synopsis of fault models at the device, gate, and function levels. Then, we introduce the basic methods available to the designer of fault tolerance measures by surveying redundancy techniques. The majority of this paper discusses fault detection, which is the discovery of a fault before it delivers errant data to the rest of the system. We examine techniques of fault detection that use space, time, and information redundancies. Along with these redundancy measures, we also investigate algorithm-based fault tolerance in VLSI components. After discussing large-scale processor-level implementations of fault detection, we describe fault tolerance in automated VLSl production systems.After our treatment of the detection of errors and faults, we examine the other areas of fault tolerance in VLSI: reconjiguration of the system and recovery of system operation. We look into the issues involved in reconjiguration after discover?/ of a fault in fabrication or in operation. Our time here is spent generally in VLSI arrays. We conclude our discussion offault tolerance in VLSl with an overview of the on-chip recovery capabilities of a VLSl microprocessor.

SEU tolerant device, circuit and processor design

“…Backward error recovery can be defined as the capability of a system to return to a consistent state that existed before it failed; a checkpoint is then defined as a consistent state from which the execution can be restarted. 18 …”

“…The use of residue coding schemes for fault tolerance has received very limited application due to the high overhead requirement for pre-multiplying input variables, limited correction capabilities, and lack of capability for general computational operations. 18 In the most common form of spatial or modular redundancy is Triple Modular Redundancy (TMR), a fault in an individual module is corrected by the action of a voter through the majority consensus, or two-out-of-three, voting rules. The individual modules may consist of basic functions such as memory elements, D-flip-flops, or latches, and more complex logic blocks such as state machines or highly complex logic functions; including complete processing functional blocks, or entire subsystems.…”

An optimal single error locating TSC-TMRsystem

“…Circuits that implement this type of coding technique are generally called totally self-checking (TSC) circuits. TSC checkers can be employed in VLSI system design for fault detection (Peercy and Banerjee 1993). Self-checking designs for Motorola 68000 and Intel i8080 processors have been accomplished through the addition of TSC blocks (external methods).…”

Faults, Error Bounds and Reliability of Nanoelectronic Circuits

“…While some of the faults are difficult to model, stuck-at faults are the most widely used models since a great majority of faults are shorts and opens, which lead overwhelmingly to stuckat-1's or stuck-at-0's [14]. Shorts in interconnects are actually bridge faults that create a short between two or more lines, and opens in interconnects are assumed to behave as "soft" stuck-at-1's or stuck-at-0's [15].…”