Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips

Abstract

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values. © 1982-2012 IEEE

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

“…Because the previous works on link-failure-aware NoC topology generation did not consider the VFI regime, we evaluate the proposed method with FTTG [16] and mesh topology (MESH) by configuring a VFI environment that is the same as ours. With four multimedia applications, namely the VOPD, MPEG-4, D_38 [21], and H.264 with 64 nodes from MCSL [22], as benchmark, we evaluate the energy consumption, latency, and area using our cycle-accurate simulator based on SystemC by combining the simulation results from ORION 2.0 [23].…”

“…Thus, the methods for tolerating permanent link failures in regular topologies cannot be directly applied to custom topologies. Tosun et al proposed a fault-tolerant custom topology generation (FTTG) method with a mapping algorithm for application-specific NoC design to tolerate at least one link failure by detouring default routing path [16]. This study showed enhanced energy efficiency with reduced area overhead compared to the previous works by focusing on minimized extra routers and considering the number of cores and communication traffic patterns in mapping stage.…”

“…To prevent excessive design complexity associated with the number of ports in routers, we use typical 4-port routers which are common in 2D NoC design. Given a cluster with n-nodes, the minimum number of routers, R min is to be determined by (4) [16] (line 1-2). …”

“…The routers with two available ports can be used for inter-VFI communication, thus addressing energy efficiency and link failure simultaneously. However, the routers with only one available port cannot be used for inter-VFI communication and will be used for providing an alternative path to guarantee communication between each node (line [14][15][16][17][18][19]. Finally, network interfaces (NIs) are generated between the routers and cores to packetize the data (line 20).…”

“…In addition, the routing effectiveness and robustness achieved by utilizing the available links and routers should be assessed in the topology generation of NoCs to guarantee correct packet transmission. Whereas there have been a number of studies on NoC topologies to cope with link failures [16,17], NoC architecture with VFI regime has rarely been embraced. For link-failure-aware VFI NoC topology generation, the choice between inter-VFI and intra-VFI links should be taken into account in order to optimize the link reliability and energy consumption.…”