A joint optimization method for NoC topology generation

Li, Yonghui; Wang, Kun; Gu, Huaxi; Yang, Yintang; Su, Nan; Chen, Yawen; Zhang, Haibo

doi:10.1007/s11227-018-2339-0

Cited by 7 publications

(4 citation statements)

References 34 publications

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“…For decades, the optimization and generation of network topologies has been an essential problem across many fields such as telecommunications [30,46], electricity distribution, gas pipelines, integrated circuit design [81,33,59] and, recently, machine learning [82,3]. With the advent of complex distributed computing architectures within cars, planes, and modern data centers, the problem has seen new instances in computer networks.…”

Section: Topology Generationmentioning

confidence: 99%

“…Their multi-step approach involves generating an initial topology and iteratively improving the solution until a suitable candidate platform is achieved. More recently, Li et al [59] clustered intra-chip cores with heavy communication, creating a topology based on core clusters and network growth rules. They used a genetic algorithm to optimize the SoC layout for power and area efficiency.…”

Section: Topology Generationmentioning

confidence: 99%

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Exploring Trade-offs in Concept Design of Integrated Modular Avionic Platform Configurations : Topology Generation, Resource Adequacy, and Dependability

Saar de Moraes

2024

Linköping Studies in Science and Technology. Dissertations

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Modern aircraft heavily depend on computer systems to carry out various tasks. From managing flight surfaces and engines to processing radar and imagery data and facilitating communication with other aircraft and ground stations, computers are involved in almost every aspect of an aircraft's operation. These computer systems, known as Integrated Modular Avionics (IMA) systems, have long life cycles that span several decades and undergo regular updates. Despite this, a significant portion of the overall life cycle costs is determined very early in the life cycle, in the concept design phase.Thank you, Tâmara and Rodrigo, for your friendship, our ski trips, and for making me feel at home despite being far from our beloved state in southern Brazil. Thank you, Letícia and Natália, for your friendship and for reminding me that I can still feel as young as you are. To my other Brazilian friends, Amanda, André (both), Gustavo, Daiane, Priscila, Fabricio, Carlos, and Bianca, thank you for all the uncountable moments we have shared.To Veronika, Emma, and Irene: I want to express my gratitude for our enjoyable moments. Thank you for providing a much-needed break from my studies and papers.Lastly, I would like to express my gratitude to my friends in Brazil. Despite the great distance, you kept in touch, offered encouragement during difficult times, and were present when I needed you. Thanks to Gabrieli, Camila, Roberta, Giovana, and Gisele for always making the time to meet me when I visit.

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Section: Topology Generationmentioning

confidence: 99%

Section: Topology Generationmentioning

confidence: 99%

Exploring Trade-offs in Concept Design of Integrated Modular Avionic Platform Configurations : Topology Generation, Resource Adequacy, and Dependability

Saar de Moraes

2024

Linköping Studies in Science and Technology. Dissertations

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“…Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al studied that, in contrast to normal beliefs, NoCs suffer from certain physical constraints, which lead to highly performance reduction.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

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Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

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“…From the perspective of low hop count and high energy efficiency of NoC topology, researchers have carried out in application-specific topology and hierarchical topology respectively. Some previous studies [15], [5], [4], [16], [17], [18] have proposed topology generation methods of applicationspecific NoCs. A series of performance-driven custom topologies were constructed for application requirements.…”

Section: Introductionmentioning

confidence: 99%

Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems

Ruan

et al. 2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this paper, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. Firstly, we propose a method to generate brain-network-inspired topologies with limited scalefree and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired NoCs generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.

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A joint optimization method for NoC topology generation

Cited by 7 publications

References 34 publications

Exploring Trade-offs in Concept Design of Integrated Modular Avionic Platform Configurations : Topology Generation, Resource Adequacy, and Dependability

Exploring Trade-offs in Concept Design of Integrated Modular Avionic Platform Configurations : Topology Generation, Resource Adequacy, and Dependability

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems

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