Fault tolerant system design and SEU injection based testing

Straka, Martin; Kastil, Jan; Kotásek, Zdenĕk; Mičulka, Lukáš

doi:10.1016/j.micpro.2012.09.006

Cited by 32 publications

(15 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An on-demand triggered scrubbing technique was proposed in [8] that offers fast recovery time by exploiting DMR and or TMR at different granularities for fault detection and masking. Straka et al [9] proposed the use of online checkers or TMR for detecting faults and an on-demand scrubbing methodology orchestrated by a partial reconfiguration controller for reconfiguring the faulty module only. A novel scrubbing method that reduces the Mean Time to Repair (MTTR) by 30% based on the exploitation of the non-uniform distribution of the critical bits of the configuration memory, was suggested in [10].…”

Section: Related Workmentioning

confidence: 99%

Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs

Michail

Bouganis

2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

Abstract-This paper presents an area-driven FieldProgrammable Gate Array (FPGA) scrubbing technique based on partial reconfiguration for Single Event Upset (SEU) mitigation. The proposed method is compared with existing techniques such as blind and on-demand scrubbing on a novel SEU mitigation framework implemented on the ZYNQ platform, supporting various SEU and scrubbing rates. Our solution achieves 22% higher availability on average with 13% less data transfers from a Double Data Rate Type 3 (DDR3) memory when compared with a blind scrubbing approach for a second order polynomial evaluation function. The comparison with an existing on-demand scrubbing technique shows that our approach has 35% lower area with a 4.7% lower availability for the same case study.

show abstract

Section: Related Workmentioning

confidence: 99%

Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs

Michail

Bouganis

2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

View full text Add to dashboard Cite

show abstract

“…To reduce the area overhead caused by the voters/checkers, some approaches [14]- [16] apply redundancy techniques not only at the granularity of the single flip-flop (as in [13]) but at the coarser granularity. Moreover, the periodic scrubbing has been replaced with a partial on-demand reconfiguration triggered by appropriate error detection signals.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the periodic scrubbing has been replaced with a partial on-demand reconfiguration triggered by appropriate error detection signals. Finally, other solutions optimize the partial reconfiguration recovery time [15], or consider also permanent faults [16], These approaches require an additional (internal or external) controller to handle the reconfiguration process, which is usually implemented by an internal microcontroller to achieve higher reconfiguration speed. To reduce area overhead and power consumption, [16] presents a customized hardware solution for the reconfiguration process.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a self-healing processor on SRAM-based FPGAs

Psarakis

Vavousis

Bolchini

et al. 2014

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

View full text Add to dashboard Cite

This paper presents an approach to design and implement a soft-core processor on SRAM-based FPGAs able to autonomously deal with the occurrence of soft errors; state-of-the-art area-replication strategies are coupled with dynamic partial reconfiguration to detect faults and to consequently repair them. The reconfiguration process is performed by the processor itself using a minimum set of "critical" instructions and the logic responsible for their execution is hardened, to enable the self-healing property. The methodology is applied to the OpenRISC processor, evaluating costs and benefits

show abstract

“…A variety of mitigation techniques have been developed to achieve an SEU immune circuit [2,[4][5][6][7]. Mostly, redundancy is at the heart of these fault tolerance methods.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA

Gosheblagh¹,

Mohammadi²

2013

IJCA

View full text Add to dashboard Cite

SRAM based FPGAs are attracting considerable interest especially in aerospace applications due to their high reconfigurability, low cost and availability. However, these devices are strongly susceptible to space radiation effects which are able to cause unwanted single event upsets (SEUs) in the configuration memory. In order to mitigate the SEU effects, various methods have been investigated in literatures. Fault injection methods are required to evaluate the efficiency of the hardening techniques. This paper has proposed a dynamic partial reconfiguration based fault-injection platform (DPR-FIP) for emulating the SEU faults in FPGA configuration memory. Besides the SEU faults, DPRFIP tool supports cumulative SEU, multi-event upset, and single event transient faults in combinational parts and flip-flops.

show abstract

Fault tolerant system design and SEU injection based testing

Cited by 32 publications

References 9 publications

Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs

Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs

Design and implementation of a self-healing processor on SRAM-based FPGAs

Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA

Contact Info

Product

Resources

About