Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

Bhanu, P. Veda; Kulkarni, Pranav Venkatesh; Soumya, J

doi:10.1145/3269983

Cited by 16 publications

(29 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This has motivated us to consider the ILP and PSO methodologies for fault-tolerant mapping of applications onto Torus topology. The faulttolerant application-mapping onto Mesh-based NoC has been addressed in the literature [10], [13]- [16]. Among these one of our previous works [16] has shown significant improvements in the performance parameters in terms of communication cost.…”

Section: Motivationmentioning

confidence: 99%

“…The faulttolerant application-mapping onto Mesh-based NoC has been addressed in the literature [10], [13]- [16]. Among these one of our previous works [16] has shown significant improvements in the performance parameters in terms of communication cost. However, the formulations (ILP and PSO) proposed in one of our previous works [16] is limited to Mesh topology only.…”

Section: Motivationmentioning

confidence: 99%

“…Among these one of our previous works [16] has shown significant improvements in the performance parameters in terms of communication cost. However, the formulations (ILP and PSO) proposed in one of our previous works [16] is limited to Mesh topology only. Due to the structural changes in the Torus topology, the formulations proposed for Mesh will not be applicable to it.…”

Section: Motivationmentioning

confidence: 99%

“…Therefore, there is a significant difference between the Mesh and Torus topologies. The major difference is in the formulation of objective function and fitness function using our previously proposed methodologies ILP and PSO [16]. The experimentation has been carried out to see the difference between the mapping information obtained for Mesh and Torus topologies using our approaches (ILP and PSO).…”

Section: Motivationmentioning

confidence: 99%

“…As mentioned above, with the change in the interconnection pattern between the routers in the topology, the performance of an application is varied from one topology to other. The primary goal of this work is to analyse the efficiency of the fault-tolerant application mapping onto Torus topology using our approaches (ILP, PSO) [16] and the approaches [10], [17]- [19]. The fault-tolerant spare core mapping (FSCM) techniques proposed by the same group of authors in [10], [17]- [19] considered the node average distance (NAD) region and map the spare core in the center of the NAD region.…”

Section: Motivationmentioning

confidence: 99%

See 4 more Smart Citations

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

et al. 2021

Self Cite

View full text Add to dashboard Cite

In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper presents the flexible placement of spare core onto Torus topology-based NoC design by considering core faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing algorithm, runtime fault injection model, and fault-tolerant placement of spare core onto Torus topology using an FPGA. Experiments have been done by taking different multimedia and synthetic application benchmarks. This has been done in both static and dynamic simulation environments followed by hardware implementation. In the static simulation environment, the experimentations are carried out by scaling the network size and router faults in the network. The results obtained from our approach outperform the methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size, our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of the proposed approach over the approaches presented in the literature.

show abstract

Section: Motivationmentioning

confidence: 99%