Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

Bhanu, P. Veda; Govindan, Rahul; Kattamuri, Plava; Soumya, J; Cenkeramaddi, Linga Reddy

doi:10.1109/access.2021.3066537

Cited by 11 publications

(3 citation statements)

References 28 publications

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“…This scheme reduces the overall latency and the energy of the hybrid NoC and optimizes the overall mapping. P.V Bhanu et al, [9] proposed a technique to provide a fault-tolerant system and verified it through both simulations and FPGA validation. Firstly, the mapping of an application by considering the fault-tolerant mechanism for a Torus topology performed through ILP and PSO.…”

Section: Related Workmentioning

confidence: 99%

An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip

Kumar

Reddy²

2022

Wireless Pers Commun

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The evolution of the components embedded on a single chip is growing faster day by day, resulting in a considerable impact on the performance metrics and communication between the cores in the NoC architecture. So, to overcome such issues, it is important to provide an efficient mapping between the cores, such that the communication between them increases. To improve the performance of a network, throughput and latency also play a significant role. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM. In this algorithm, based on the minimum Core Average Distance (CAD) the mapping region is finalized, ensuring the overall mapping area reduced. The PE's mapped according to the minimum communication energy in the selected mapping region. This research evaluated a set of embedded applications, which reveals a reduction in latency at 12.3% against BBPCR and 8.4% against SBMAP. The simulation time reduces at an average of 19% against BBPCR and 9.6% against SBMAP. The throughput increases at an average of 14.5% against BBPCR and 7.8% against SBMAP and reduces the communication energy by 15.6% against BBPCR and 5.2% against SBMAP.Keywords System on Chip (SoC) • Network on Chip (NoC) • Core mapping, • Real-Time embedded applications, • Performance.

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Section: Related Workmentioning

confidence: 99%

An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip

Kumar

Reddy²

2022

Wireless Pers Commun

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“…The execution and implementation of the FPGA are completely theoretical, so it is preferred to execute the BE NoC that has been performed. The primary concern of the thesis is availability, and the least prioritized issue is execution [16]. The area of the complete structure is low, this is result of the accessible logical resources on the given FPGA [17].…”

Section: Introductionmentioning

confidence: 99%

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Patil,

Sandi

2024

IJRES

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The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

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“…However, the routing design is more complex, and routing takes up more resources. The Torus structure [ 23 ] adds ring routing to 2D-mesh, which further improves routing flexibility and consumes more resources for routing.…”

Section: Introductionmentioning

confidence: 99%

Resource-Saving Customizable Pipeline Network Architecture for Multi-Signal Processing in Edge Devices

Song

Qie

Hao

et al. 2022

Sensors

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With the development of the information age, the importance of edge computing has been highlighted in industrial site monitoring, health management, and fault diagnosis. Among them, the processing and computing of signals in edge scenarios is the cornerstone of realizing these scenarios. While the performance of edge devices has been dramatically improved, the demand for signal processing in the edge side has also ushered in explosive growth. However, the deployment of traditional serial or parallel signal processing architectures on edge devices has problems such as poor flexibility, low efficiency, and low resource utilization, making edge devices unable to exert their maximum performance. Therefore, this paper proposes a resource-saving customizable pipeline network architecture with a space-optimized resource allocation method and a coordinate addressing method for irregular topology. This architecture significantly improves the flexibility of multi-signal processing in edge devices, improves resource utilization, and further increases the performance potential of edge devices. Finally, we designed a comparative experiment to prove that the resource-saving and customizable pipeline network architecture can significantly reduce resource consumption under the premise of meeting real-time processing requirements.

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Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA

Cited by 11 publications

References 28 publications

An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip

An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

Resource-Saving Customizable Pipeline Network Architecture for Multi-Signal Processing in Edge Devices

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