Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs

Tambara, Lucas Antunes; Tarrillo, Jimmy; Kastensmidt, Fernanda Lima; Sterpone, Luca

doi:10.1007/978-3-319-14352-1_9

Cited by 2 publications

(1 citation statement)

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“…Thus, when a fault changes the state of an SRAM cell, this event is referred as SEU [7]. In other words, SRAM-based FPGAs are more prone to soft errors since a radiation strike in a configuration memory has a permanent effect on the functionality of the mapped design [8].…”

Section: Introductionmentioning

confidence: 99%

An Improved Frame Level Redundancy Scrubbing Algorithm for SRAM based FPGA

Haruna¹,

Abubilal²,

Salawudeen³

2017

IJCA

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The use of Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. Therefore, an improved Frame Level Redundancy (FLR) algorithm that uses Cyclic Redundancy Check (CRC) as an error detection technique for configuration memory scrubbing, is developed as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.

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Section: Introductionmentioning

confidence: 99%