FPGA-Centric Design Process for Avionic Simulation and Test

Atitallah, Rabıe Ben; Viswanathan, Venkatasubramanian; Bélanger, Nicolas; Dekeyser, Jean-Luc

doi:10.1109/taes.2017.2733858

Cited by 11 publications

(2 citation statements)

References 24 publications

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“…Furthermore, provided that our design is supported with a COTS platform using standard-based Ethernet physical interfaces, it can also achieve a far superior bandwidth of up to 1 Gb/s. In addition, as indicated in [63], it represents a comprehensive platform for testing, simulating, and verifying the integration of a complete avionics system. Thus, our solution achieved enhanced levels of performance and interoperability.…”

Section: Discussionmentioning

confidence: 99%

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Sanchez-Garrido

Aparicio

Ramírez

et al. 2021

IEEE Trans. Aerosp. Electron. Syst.

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The design of the aerospace systems for future aircraft requires the identification of new, suitable communication infrastructures that can overcome the limitations that often come with the use of the legacy, albeit well-proven, protocols that are routinely integrated in aerospace. This allows us to overcome the bandwidth constraints, large deployment costs or the lack in flexibility of other alternatives, like Spacewire, or legacy systems such as the MIL-STD-1553B bus. These protocols can be replaced with new technologies that can fulfill the greater real-time and interconnectivity demands of advanced scientific probes or manned spacecraft. The advent of the new microlauncher systems has all but confirmed this trend. In this context, we describe the design and implementation of a time-sensitive networking (TSN) bus for the avionics of the Miura 1 suborbital microlauncher. TSN represents an appropriate interface for this type of platform given its ability to provide the determinism and reliability expected in space-grade systems in combination with the higher data rates (Gigabit Ethernet) and greater flexibility of standard Ethernet. This has resulted in a TSN platform developed by Seven Solutions S.L. based on the commercially available Zynq-7000 devices from Xilinx. Thus, our design features a light-footprint field-programmable gate array (FPGA) architecture powered by a real-time executive for multiprocessor systems (RTEMS) operating system, which is currently pending its certification from the European Space Agency (ESA) for space applications. All these elements have been successfully integrated and validated for the avionics of the Miura 1 sounding rocket, which represents an illustrative case that verifies their applicability to similar scenarios.

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Section: Discussionmentioning

confidence: 99%

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Sanchez-Garrido

Aparicio

Ramírez

et al. 2021

IEEE Trans. Aerosp. Electron. Syst.

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show abstract

“…Then, in stage 4, the timing analysis is performed with the TimeQuest Timing Analyzer to verify circuit performance and detect possible timing violations. The TimeQuest analyzer determines the timing relationships and checks arrival times against the times required to verify timing [21][22][23]. If the report describes that there is no violation of the requirements imposed by the designer, the project is almost finished.…”

Section: Hardware Developmentmentioning

confidence: 99%

Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a Field Programmable Gate Array

et al. 2021

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Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation; however, their high costs have led to the increasing use of more affordable and reconfigurable technologies. In this context, many logic blocks and storage elements make the Field Programmable Gate Array (FPGA) an ideal device to perform RTDS. This work proposes a technique to embed a real-time digital simulator in an FPGA through Hardware Description Language (HDL) since it provides liberty in the architecture choice and no dependency on commercial ready-made hardware–software packages. The approach proposed focuses on system design developing with expression tree graph, synthesizing and verifying, prioritizing the performance and design accuracy concerning area and power consumption. Thus, the result acquisition occurs at a time step considered in real-time. A simulation of a direct current (DC) motor speed control has been incorporated into this work as an example of application, which includes the embedding and simulation of the electric machine and its drive system. Performance tests have shown that the developed simulator is real-time and makes possible realistic analysis of the interaction between the plant and its control. In addition, an idea of the hardware requirement for real-time simulation is proposed based on the number of mathematical operations.

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Low power high speed FPGA design of lossless medical image compression using optimal deep neural network

Sharma

2023

Multimed Tools Appl

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FPGA-Centric Design Process for Avionic Simulation and Test

Cited by 11 publications

References 24 publications

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a Field Programmable Gate Array

Low power high speed FPGA design of lossless medical image compression using optimal deep neural network

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