Fault-tolerant digital filters on FPGA using hardware redundancy techniques

Mallavarapu, Prasanth; Upadhyay, Har Narayan; Rajkumar, G.; Elamaran, V.

doi:10.1109/iceca.2017.8212811

Cited by 8 publications

(8 citation statements)

References 7 publications

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“…In the case of moving average FIR filters, for example, the parallel and transposed structures were not investigated. There are so many significant comparisons among the power dissipation data because the filters were deployed in an FPGA device [ 55 ]. Instead, the filters can be used in application-specific integrated circuits (ASIC) for better results (space, speed, and power).…”

Section: Resultsmentioning

confidence: 99%

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Jerard

Thilagaraj

Pandiaraj

et al. 2021

Journal of Healthcare Engineering

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Recent advances in electronics and microelectronics have aided the development of low-cost devices that are widely used as well-being or preventive monitoring devices by many people. Remote health monitoring, which includes wearable sensors, actuators, and modern communication and information systems, offers effective programs that allow people to live peacefully in their own homes while also being protected in some way. High-frequency noise, power-line interface, and baseline drift are prevalent during the data-acquisition system of an ECG signal, and they can limit signal understanding. They (noises) must be isolated in order to provide an appropriate diagnostic of the patient. When removing high-frequency components (noise) from an ECG signal with an FIR filter, the critical path delay increases considerably as the filter's duration increases. To reduce high-frequency noise, simple moving average filters with pipelining and look-ahead transformation techniques are extensively used in this study. With the use of pipelining and look-ahead techniques, the only objective is to increase the clock speed of the designs. The moving average filters (conventional and proposed) were created on an Altera Cyclone IV FPGA EP4CE115F29C7 chip using the Quartus II software v13.1 tool. Finally, performance metrics such logic elements, clock speed, and power consumption were compared and studied thoroughly. The recursive pipelined 8-tap MA filter with look-ahead approach outperforms the other designs (685.48 MHz) in this investigation.

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Section: Resultsmentioning

confidence: 99%

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Jerard

Thilagaraj

Pandiaraj

et al. 2021

Journal of Healthcare Engineering

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“…As mentioned earlier, the redundancy technique is a very popular method that can be implemented right from the design stage to improve the fault tolerance. The redundancy is mainly divided into three types: (1) hardware [20][21][22], (2) time [23], and (3) information redundancy [24]. Figure 2 depicts a typical block diagram of the FSMs, which consists of a state register, next state logic, and output logic [17,18].…”

Section: Fault-tolerant Techniquesmentioning

confidence: 99%

Section: Fault-tolerant Techniquesmentioning

confidence: 99%

“…Hardware redundancy [20][21][22] duplicates the original design by as many as the redundancy number R. Based on the majority votes, the final output is determined from among the R outputs of different hardware. For the case of R = 3, Figure 3 shows the example of a block diagram of a dk17 FSM with hardware redundancy [20][21][22], where the gray color indicates the additional hardware resources compared to the typical FSM structure. Although hardware redundancy [20][21][22] is simple to design, as shown in Figure 3, it demands the same amount of additional hardware as the redundancy number R. The hardware complexity increases substantially when a large redundancy number R is applied.…”

Section: Fault-tolerant Techniquesmentioning

confidence: 99%

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Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Park

Yoo

2020

Electronics

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A differential fault tolerance encoding is presented for finite state machines (FSMs) to improve their area efficiency. As the manufacturing technology for semiconductors continues to scale down, the probability of the occurrence of unexpected faults in integrated circuits has been increasing. Because an FSM controls an entire digital circuit, the faults in FSMs should be carefully addressed. Whereas the previous encoding applies a fault tolerance scheme to all the states in an FSM, the proposed encoding applies a fault tolerance scheme to only specific states depending on their importance. Compared with the previous complete fault tolerance encoding, the proposed encoding provides a comparable failure probability with a small hardware by applying the fault tolerance scheme differently to each state. The proposed method improves the area efficiency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Consequently, the proposed method can provide a flexible solution by applying the fault tolerance differently depending on the importance of the states.

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“…Such an approach works for hardware [1]. This also applies to the application of FPGA [2]. In the case of software, it makes no sense simply to copy programs or their modules.…”

Section: Introductionmentioning

confidence: 99%

Implementation of decision‐making algorithms in redundant systems on FPGA

Сарамуд¹,

Лосев²,

Petetskaya³

2022

Proceedings of the v International Workshop on Modeling, Information Processing and Computing (MIP: Computing-v 2022)

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The paper describes the problem of creating fault-tolerant real-time control systems. The authors describe methods for improving the reliability of control systems for both hardware and software. The features of the system operation in real time are presented. The paper considers various versions of hardware platforms for real-time operation are such as CPU applying RTOS, FPGA, ASIC. The peculiarities of applying FPGA and developing software for it are outlined. The main blocks that make up the FPGA are represented. The hardware platform for prototype implementation is proposed. The authors opt to follow myRIO-1900 based on SoC Xilinx Zynq-7010 as it contains FPGA, CPU with RTOS implementation for it. A new approach is proposed. It combines the implementation of a decision-making block in control systems by means of a real-time operating system running on a CPU and a special FPGA that implements watchdogs and decision-making algorithms in multiversion systems. Watchdog on the FPGA monitors the main decision block in the RTOS. It should provide a response within a specified period of time. If this does not happen, it starts a spare decision block implemented on the FPGA. It is guaranteed to make a decision in one clock cycle of the FPGA. This approach will improve the overall reliability of fault-tolerant control systems without significantly increasing their cost.

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Fault-tolerant digital filters on FPGA using hardware redundancy techniques

Cited by 8 publications

References 7 publications

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

Implementation of decision‐making algorithms in redundant systems on FPGA

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