Fault Tolerance on NoCs

Abstract

Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on shared buses, because it provides higher communication performance.The probability of failure increases in this systems, due to these great advances in integration scales and the increasing number of components on chip. Therefore Fault Tolerance will become a key aspect on designing the near future VLSI SoC, and especially on their interconnection Network on Chip (NoC). This paper focuses on describe the particular aspects of NoCs, and the proposed fault-tolerant strategies for NoCs.

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

“…A key element in comparing routing between mesh and circulant topologies is network load testing; that is, the study of the possibility of building routes in case of the failure of a certain number of nodes in NoCs [7,45].…”