Fault partitioning issues in an integrated parallel test generation/fault simulation environment

Patil, S.; Banerjee, P.

doi:10.1109/test.1989.82360

Cited by 49 publications

(21 citation statements)

References 19 publications

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“…This technique will be shown to be an improvement on the vector broadcasting technique proposed in [17].…”

Section: Deterministic Test Pattern Generation Uses One Of Numerous Amentioning

confidence: 99%

“…There are several methods available to parallelize ATPG [2,3]. These methods include fault partitioning [4,5,6,7,8,9,10], heuristic parallelization [8,11], search space partitioning [2,7,12,13], algorithmic partitioning [7], and topological partitioning [14,15,16]. Of these methods, the simplest to implement is fault partitioning, which divides the fault list across various processors.…”

Section: Deterministic Test Pattern Generation Uses One Of Numerous Amentioning

confidence: 99%

“…Dynamic load balancing allows the fault list to be repartitioned at runtime when workload imbalances are detected. As demonstrated in [4,5], dynamic load balancing can significantly improve the performance of fault partitioned ATPG by minimizing processor idle time.…”

Section: Dynamic Load Balancingmentioning

confidence: 99%

“…This research compares two methods for eliminating this problem: detected fault broadcasting [18] and generated vector broadcasting [17]. Both methods were added as options to the base PP-TGS system.…”

Section: Detected Fault and Generated Vector Broadcastingmentioning

confidence: 99%

“…, (4)(5)(6)(7)(8)(9)(10) and substituting the derivative of equation (4-9) in equation (4-10) yields:…”

Section: Analysis Of Dynamic Load Balancingmentioning

confidence: 99%

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An analysis of fault partitioned parallel test generation

Wolf

Kaufman

Klenke

et al. 1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an active area of research.The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors. Each individual processor then performs the normal test generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. An earlier approach to reducing this redundant work involved transmitting generated test vectors among the processors and re-fault simulating them on each processor. This paper presents a comparison of the vector broadcasting approach with the simpler and more effective approach of fault broadcasting. In fault broadcasting, fault simulation is performed on the entire fault list on each processor. The resulting list of detected faults is then transmitted to all the other processors. The results show that this technique produces greater speedups and smaller test sets than the test vector broadcasting technique. Analytical models are developed which can be used to determine the cost of the various parts of the parallel ATPG algorithm. These models are validated using data from benchmark circuits.1

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“…This technique will be shown to be an improvement on the vector broadcasting technique proposed in [17].…”

Section: Deterministic Test Pattern Generation Uses One Of Numerous Amentioning

confidence: 99%

Section: Deterministic Test Pattern Generation Uses One Of Numerous Amentioning

confidence: 99%

Section: Dynamic Load Balancingmentioning

confidence: 99%

Section: Detected Fault and Generated Vector Broadcastingmentioning

confidence: 99%

“…, (4)(5)(6)(7)(8)(9)(10) and substituting the derivative of equation (4-9) in equation (4-10) yields:…”

Section: Analysis Of Dynamic Load Balancingmentioning

confidence: 99%

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An analysis of fault partitioned parallel test generation

Wolf

Kaufman

Klenke

et al. 1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Parallel VLSI test in a shared-memory multiprocessor

Gil

Ortega

Montoya

2000

Concurrency: Pract. Exper.

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SUMMARYThis paper presents three parallel procedures implemented in a shared-memory multiprocessor to generate the patterns that allow the testing of digital circuits. The implementation of these procedures in a multiprocessor uses the system memory better than in a distributed-memory multicomputer, since it is not necessary to store the circuit structure in the local memory of each processor, besides other common structures. The parallel test generation procedures are based on a new sequential algorithm which mixes both the Boolean difference and digital spectral techniques. It is thus different from other methods proposed that deal with the parallelization of test generation algorithms that carry out an implicit enumeration of the input pattern space. The first procedure distributes the set of faults using a backtracking procedure starting from a primary output and allocating a similar number of lines to each processor. The second procedure distributes the set of faults among the processors taking into account the distance from each line to its nearest primary output; it then applies the algorithm to generate the test pattern with some modifications. The third procedure uses a circuit partitioning procedure which allows similar sized parts of the circuit to be assigned to each processor while communications between processors are minimized. The experimental results obtained when the procedures are applied to the usual benchmark circuits (the ISCAS set) show figures for speedup better than in a multicomputer, although fewer processors are used.

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A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method

Yeh

Huang

2009

Algorithms and Architectures for Parallel Processing

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Fault partitioning issues in an integrated parallel test generation/fault simulation environment

Cited by 49 publications

References 19 publications

An analysis of fault partitioned parallel test generation

An analysis of fault partitioned parallel test generation

Parallel VLSI test in a shared-memory multiprocessor

A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method

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