A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method

Yeh, Kuen-Wei; Wu, Ming-Hung; Huang, Jiun-Lang

doi:10.1007/978-3-642-03095-6_35

Cited by 10 publications

(7 citation statements)

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“…As mentioned before, many previous works like [1] [2] have used fault broadcasting to deal with the test-inflation problem. However, it is not sufficient when fault dropping and test generation happen simultaneously on an identical fault as shown in Figure 2(a).…”

Section: A Concurrent Interruptionmentioning

confidence: 99%

“…Krishnaswamy et al in [8] parallelized fault simulation but overlooked test generation. Yeh et al in [2] demonstrated parallelism in test generation as well as fault simulation, achieving sub-linear speedup, but suffers from severe test inflation. Wolf et al in [10] parallelized ATPG completely but did not implement test compaction to suppress test inflation.…”

Section: Introductionmentioning

confidence: 98%

“…However, one fatal limitation for a parallel ATPG is test inflation [1] [2], which is illustrated by Figure 1. Test inflation is an inherent problem of parallel ATPG and to overcome test inflation, a conventional technique, fault broadcasting [13] [14], is often used.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…By its communication protocol, a parallel computing architecture can be classified into: shared-memory system and message-passing system. Both parallel computing systems provide additional computing power and thus are used in [1] [2][10] to speed up ATPG recently.Common strategies used in parallel ATPG include fault parallelism, heuristic parallelism, search-space parallelism, algorithmic parallelism, and circuit parallelism. Fault parallelism [4] divides all faults among available processors and each processor generates tests for its corresponding faults.…”

mentioning

confidence: 99%

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Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation

Huang

Lin

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves ∼0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits. I. . INTRODUCTIONAs VLSI designs continue to grow in size and complexity, the demand for faster ATPG arises for their verification testing. The conventional ATPG algorithm running on single processor has reached its bottleneck and become unsustainable to generate quality tests effectively for modern designs. The rapid development of multi-core processors enables the possibility of parallel computing and emerges to be a solution for scaled designs. By its communication protocol, a parallel computing architecture can be classified into: shared-memory system and message-passing system. Both parallel computing systems provide additional computing power and thus are used in [1] [2][10] to speed up ATPG recently.Common strategies used in parallel ATPG include fault parallelism, heuristic parallelism, search-space parallelism, algorithmic parallelism, and circuit parallelism. Fault parallelism [4] divides all faults among available processors and each processor generates tests for its corresponding faults. For heuristic parallelism [5], each processor employs a distinctive ATPG algorithm to generate a test for the same fault. Search-space parallelism [5] allows the processors to work collectively in finding a test for a single fault by dividing search space into discrete pieces and let each processor work on these search spaces simultaneously. ATPG algorithms are divided into fine- Fig. 1. Test-inflation problem in parallel ATPG grained tasks and processors work in parallel on each task in algorithmic parallelism [6]. For circuit parallelism [7], the circuit is divided into disjoint sub-circuits and each processor will perform ATPG operations on its respective part.Although various parallelism approaches were proposed, the core of parallel ATPG does not vary with these approaches and involves only two major operations: test generation and fault simulation. Krishnaswamy et al. in [8] parallelized fault simulation but overlooked test generation. Yeh et al. in [2] demonstrate...

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Section: A Concurrent Interruptionmentioning

confidence: 99%