Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits

Abstract

Abstract-Reversible circuits are an attractive computation alternative as they build the basis for many emerging technologies such as quantum computation or low power design. Since first physical realizations of reversible circuits have already been presented in the past, how to efficiently test such circuits became a current research topic. Consequently, several approaches for Automatic Test Pattern Generation (ATPG) have been presented in the past.However, the order in which the respective faults are targeted has a significant effect on the resulting test size. While determining good fault orderings has intensely been considered for the test of conventional circuits, according strategies for reversible circuits have not been evaluated yet. This is done in this paper. To this end, a fault ordering scheme is presented that explicitely exploits the reversibility of the underlying circuits. Experimental results show that the proposed scheme leads to improvements of up to 65% in the size of the testset.

Building a Completely Reversible Computer

“…In this context, several separate features of reversible computing have been shown to be superior to classical computing model. For instance information reversibility has been effective for lost state recovery in sequential logic [14], testing reversible circuits is much simpler [26], adiabatic charging [11]) reduces power of computing.Despite the fact that, in theory, reversible computing is a concept that offers solutions at various levels of implementation, it has not captured the mainstream research and development. .…”