Fault list compression for efficient analogue and mixed-signal production test preparation

Abstract

Accurate test effectiveness estimation for analogue and mixed-signal Systems on Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. In this paper we present a novel fault list compression technique that defines a stratified fault list, build with a set of representative faults (RFs), one per stratum. Criteria to partition the fault list in strata, and to identify RFs are presented and discussed. A fault representativeness metric is utilized, which is based on an error probability. The proposed methodology allows a tradeoff between fault list compression and fault representation accuracy that may be optimized for each test preparation phase. The methodology is independent of the chosen fault models and it is tested on cells with and without feedback. Fault representativeness evaluation is presented by applying the methodology to an industrial DC-DC converter. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

“…The time-domain algorithm for fault simulation work in two iterative shells. One is the outer iteration that steps through [22] Fault modeling and simulation [23] Parametric fault simulation 2011 [24] Efficient time-domain simulation [25] Fault equivalence 2011 [26] Fault sensitivity analysis [27] Parametric variation 2011 [28] Fault sensitivity analysis [29] Behavioral level simulation 2012 [30] Fast fault simulation [31] Behavioral level simulation 2012 [32] Layout level defect injection [33] Fault sensitivity analysis 2012 [34] Inductive Fault analysis [35] High-level fault simulation 2013 [36] Numerical-based method [37] Parallel fault simulation 2013 [38] Inductive fault analysis [39] Tool for fault simulation 2013 [40] High-level fault simulation [9] Behavioral level simulation 2014 [41] Fault list compression technique [42] Multi-level hierarchical analogue fault simulation 2014 [43] Practical random sampling [44] Fast fault simulation for nonlinear analog circuits 2014 [45] Impedance calculation [46] [77] Macro modeling of analog components [78] Behavioral level fault simulation 2018 [79] Simulation at high abstraction level [80] Systematic method 2018 [81] Random sampling [82] Mixed-mode fault simulation 2019 [2] Likelihood-weighted random sampling of defects [83] Test point selection 2019 [84] Industrial Analog fault simulator [85] Analog fault injection and simulation interface 2019 ...…”

“…Grouping can be performed by using different strategies related to the simulation method. Various authors have proposed several algorithms for grouping faults [21], [25], [34], [41], [46], [48], [54], [60], [65], [92]. The ultimate goal of grouping is to reduce the number of faults that must be simulated by creating clusters of similar/related faults and simulating just one representative fault for each cluster.…”

“…In [41], a fault list compression using the stratified fault grouping technique has been proposed. This approach used stratified fault grouping for the identification of representative faults.…”

“…Fault simulation using high-level models [9], [53], [91], [29], [62], [89], [82], [35], [31], [58], [66], [74], [78], [40], [87], [55], [42], [82], [91], [56] Fault simulation using fault grouping [70], [21], [48], [46], [54], [92], [65], [41], [86], [8], [25], [60] Concurrent and parallel fault simulation [7], [51], [69], [61], [37], [51], [30] Fault sensitivity analysis [11], [75], [33], [49], [26], [28] Monte Carlo simulation [10], [47], [22] DC fault simulation [64]…”

Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression

“…The estimated value for fault coverage may then be used to evaluate the test quality and to appropriately drive DFT efforts [14]. This technique was introduced in [15] but it was limited to single output cells (voltage signals). Now we extend its applicability to multiple output cells (voltage and/or current signals).…”