Fault grading using Instruction-Execution graph

Vinutha, K. R.; Singh, Virendra; Matrosova, A.; Gaur, Manoj Singh

doi:10.1109/ewdts.2010.5742054

Cited by 4 publications

(4 citation statements)

References 9 publications

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“…Alternatively, it is possible to use test sequences that were generated as part of a simulation-based design verification process. In this case, either various metrics [11], [12], [13], [14] are suggested how to select the appropriate test sequences from the large verification test pool or selection procedures [16], [17] are proposed in order to improve the effectiveness of the existing functional test sequences.…”

Section: Related Workmentioning

confidence: 99%

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Black box delay fault models for non-scan sequential circuits

et al. 2018

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We presented nine new black box delay fault models for non-scan sequential circuits at the functional level, when the primary inputs and primary outputs are available only. We examined the suggested fault models in two stages. During the first stage of the experiment, we selected the best two fault models for further examination on the base of criterion proposed in the paper. During the second stage, we used the functional delay fault model and two black box delay fault models from the first stage for test selection. The comparison of fault coverages was carried out for transition faults. The obtained results demonstrate that transition fault coverages of tests selected based on proposed black box fault models are similar to coverages of tests selected based on functional delay fault model that uses the inner state of circuit.

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Section: Related Workmentioning

confidence: 99%

“…Vinutha et al [14] described a metric to grade the test sequence using instructionexecution graph. The metric is based on the set of registers the circuit traverses under the test sequence.…”

Section: Related Workmentioning

confidence: 99%

Black box delay fault models for non-scan sequential circuits

et al. 2018

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“…The functional test sequences are long [8] and it is very time-consuming to evaluate the quality of functional test sequences by gate-level fault simulation. Several authors [12,13,14] suggested estimating the fault coverage of functional test sequences without fault simulation.…”

Section: Related Workmentioning

confidence: 99%

“…Vinutha et al [14] described a metric to grade the test sequence using instruction-execution graph. The metric is based on the set of registers the circuit traverses under the test sequence.…”

Section: Related Workmentioning

confidence: 99%

Functional delay test generation approach using a software prototype of the circuit

Bareiša¹,

Jusas²,

Motiejūnas³

et al. 2013

COMSIS J

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The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. The faults are considered on the inputs and on the outputs of the model only. The random input stimuli are generated and selected then according to the proposed approach. The experimental results demonstrate the superiority of the delay test stimuli generated at the functional level using the introduced approach against the transition test stimuli obtained at the gate level by deterministic test generator. The functional delay test generation approach especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.

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Intelligent Fault Detection System for State Grid IoT Equipment Based on Edge Computing

Lai

Chen

et al. 2019

2019 IEEE 3rd International Electrical and Energy Conference (CIEEC)

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Fault grading using Instruction-Execution graph

Cited by 4 publications

References 9 publications

Black box delay fault models for non-scan sequential circuits

Black box delay fault models for non-scan sequential circuits

Functional delay test generation approach using a software prototype of the circuit

Intelligent Fault Detection System for State Grid IoT Equipment Based on Edge Computing

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