Fault diagnosis of TSV-based interconnects in 3-D stacked designs

Rajski, J.; Tyszer, Jerzy

doi:10.1109/test.2013.6651894

Cited by 13 publications

(4 citation statements)

References 40 publications

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“…Recent studies have highlighted the challenges associated with testing ILVs in 3D ICs, as the high ILV integration density can introduce significant overhead for conventional interconnect BIST approaches [18]. Retrofitting these approaches can require dedicated scan elements and large test application times, especially for high ILV density, and ATPGbased interconnect test methods are less effective due to limited I/O pins on one layer in an M3D IC [19].…”

Section: Related Workmentioning

confidence: 99%

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Menbari,

Rahimi,

Jahanirad

et al. 2023

Preprint

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<p> In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitate robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. </p>

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Section: Related Workmentioning

confidence: 99%

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Menbari,

Rahimi,

Jahanirad

et al. 2023

Preprint

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show abstract

“…which indicates that a session can have 0 to r TSVs, and r q=0 δ jq = 1 (13) indicating that the size of a session should be unique. For every session S j , there will be exactly one value of q for which δ jq = 1.…”

Section: Preliminaries and Motivationmentioning

confidence: 99%

“…The post-bond TSV test has been extensively studied [8], [9], [13]. After bonding TSVs are basically treated as wires.…”

Section: Introductionmentioning

confidence: 99%

Diagnostic Tests for Pre-bond TSV Defects

Zhang

Agrawal

2015

2015 28th International Conference on VLSI Design

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Pre-bond testing and defect identification of through silicon via (TSV) is extremely important for yield assurance of 3D stacked devices. Based on a recently published pre-bond TSV probing technique, this paper proposes an ILP (integer linear programming) model to generate near-optimal set of sessions for pre-bond TSV test. The sessions generated by our model identify defective TSVs in a TSV network with the same capability as that of other available heuristic methods, but with consistently reduced test time. The ILP model is shown to reduce the pre-bond TSV test time by 38.2% for pinpointing up to two faulty TSVs in an 11-TSV network. Reducing prebond TSV test time helps reduce the manufacturing cost of 3D stacked devices. This ILP model has low complexity and an example demonstration using a commercial solver takes less than 40 seconds.

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“…3D-ICs offer many significant benefits over traditional stacking with wire-bonds including small footprint, high bandwidth, lower power and heterogeneous integration [1]. It has been estimated that the switch to vertical interconnects may reduce power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent [2].…”

Section: Introductionmentioning

confidence: 99%

Pulse shrinkage based pre-bond through silicon vias test in 3D IC

Chang

Liang

2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40M Ω. The estimated design for testability area cost of our method is negligible for realistic dies. IEEE 33rd VLSI Test Symposium (VTS)978-1-4799-7597-6/15/$31.00 ©2015 IEEE

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Fault diagnosis of TSV-based interconnects in 3-D stacked designs

Cited by 13 publications

References 40 publications

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Diagnostic Tests for Pre-bond TSV Defects

Pulse shrinkage based pre-bond through silicon vias test in 3D IC

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