Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory

Lu, Shyue-Kung; Tsai, Zeng-Long; Hsu, Chun-Lung; Sun, Chi-Tien

doi:10.1109/vlsi-dat49148.2020.9196286

Cited by 1 publication

(2 citation statements)

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“…En el caso de [26], y utilizando códigos Reed-Solomon, se definen también diferentes niveles de protección. Otro ejemplo similar se puede ver en [27], en el que también se definen varios niveles de error, y a cada nivel se aplica un ECC distinto. En estos dos últimos ejemplos, el número de bits de paridad varía a medida que se necesita una mayor tolerancia a fallos, lo que implica que cuando se detecta un error, se tiene que recodificar el bloque de datos.…”

Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

“…Esta configuración está inspirada en trabajos como los presentados en [25][26][27] [28], donde los autores dividen la memoria en bloques y, en función de un mapa de bloques de fiabilidad calculado previamente, asignan un ECC diferente a cada bloque. Por ejemplo, en [26] y [27] se cambia de ECC en función de la tasa de errores, mientras que en [28] cada ECC tiene un número diferente de bits de código, dependiendo de si el bloque necesita una mayor o menor protección contra errores. En nuestro ejemplo, todos los ECC tienen el mismo número de bits redundantes.…”

Section: B Modelos Vhdl Utilizadosunclassified

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A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

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Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some contexts, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this fault-tolerant mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder and various decoders. Therefore, there is no need to re-encode the data to change the error coverage since the unique encoder and the equal redundancy are the same regardless of the fault tolerance required. In addition, we have studied the area, delay, and power consumption overheads produced by the inclusion of the redundant bits, the encoder, and the decoders of the ECC in a computer system.

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Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified