FASTrust: Feature analysis for third-party IP trust verification

Abstract

Third-party intellectual property (3PIP) cores are widely used in integrated circuit designs and it is essential to ensure their trustworthiness. Existing hardware trust verification techniques suffer from high computational complexity, low extensibility, and inability to detect implicitly-triggered hardware trojans (HTs). To tackle the above problems, in this paper, we present a novel 3PIP trust verification framework, namely FASTrust, which conducts HT feature analysis on the flip-flop level control-data flow graph (CDFG) of the circuit. FASTrust is not only able to identify existing explicitly-triggered and implicitly-triggered HTs appeared in the literature in an efficient and effective manner, but more importantly, it has the unique advantage of being scalable to defend against future and more stealthy HTs by adding new features to the system.

A game theory approach for RTL security verification resources allocation

“…Further, Fern et al (2017) precisely define suspicious unspecified functionality and formulate the detection as a satisfiability problem. FASTrust, a feature analysis method on the flip-flop level CDFG, is introduced for identifying the malicious circuits (Yao et al 2015). Those feature based methods rely on the effective HTs features and easily cause a high false positive.…”

A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits

“…Recently, a number of hardware Trojan detection methods based on circuit feature analysis have been proposed. In [17], the authors propose a HT detection method named FASTrust. They construct the flip-flop level control data flow graphs (CDFGs) in which flip-flops, primitive inputs, as well as primitive outputs are abstracted as nodes and combinational logic circuits are abstracted as directed edges.…”

“…Usually a HT is quietly hidden in its host circuit and can only be triggered in rare conditions [5]. To detect the silent HTs, currently there are three categories of method: logic testing [6]- [10], side-channel analysis [11]- [16] and feature analysis [17]- [22]. Logic testing approaches [6]- [10] attempt to generate a large number of test vectors to activate unknown HTs and propagate their effects to the output ports.…”

“…The side-channel analysis approaches detect HTs at the post-fabrication stage. In contrast, feature analysis approaches [17]- [22], in which structural features in gate-level netlist of known HTs are extracted for identification, have been proven as an effective static approach and avoid test vector generation and application. Like software virus detection paradigm, HT feature database is constructed and maintained.…”

Holistic hardware Trojan design of trigger and payload at gate level with rare switching signals eliminated

“…For the simple structures in SOP and POS, the Trojan circuits may be tracked by their structural pattern in feature analysis based detections [27,28,29,30], especially the bottom-up implementation of POS (POS-BU) where exists an AND-logic group. So we propose mixing these two structures showed in Fig.…”