A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits

Liu, Qiang; Zhao, Pengyong; Chen, Fuqiang

doi:10.1109/access.2019.2908088

Cited by 18 publications

(8 citation statements)

References 27 publications

(49 reference statements)

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“…Our learning model is trained only on the circuit's netlist and we do not use any other features other than the gate-types of each gate in C p . This deliberate restriction of our approach (i.e., to only use information available from the circuit netlist) is to ensure avoidance of cost associated with rich feature engineering pipelines that have been employed by previously proposed HT detection methods [12], [13], [15], [19], [28], preventing these methods from scaling to large circuit databases.…”

Section: Ht Trigger Detection With Gate-netmentioning

confidence: 99%

Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores

Muralidhar,

Zubair,

Weidler

et al. 2022

Preprint

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The availability of wide-ranging third-party intellectual property (3PIP) cores enables integrated circuit (IC) designers to focus on designing high-level features in ASICs/SoCs. The massive proliferation of ICs brings with it an increased number of bad actors seeking to exploit those circuits for various nefarious reasons. This is not surprising as integrated circuits affect every aspect of society. Thus, malicious logic (Hardware Trojans, HT) being surreptitiously injected by untrusted vendors into 3PIP cores used in IC design is an ever present threat. In this paper, we explore methods for identification of trigger-based HT in designs containing synthesizable IP cores without a golden model. Specifically, we develop methods to detect hardware trojans by detecting triggers embedded in ICs purely based on netlists acquired from the vendor. We propose GATE-Net , a deep learning model based on graph-convolutional networks (GCN) trained using supervised contrastive learning, for flagging designs containing randomly-inserted triggers using only the corresponding netlist. Our proposed architecture achieves significant improvements over state-of-the-art learning models yielding an average 46.99% improvement in detection performance for combinatorial triggers and 21.91% improvement for sequential triggers across a variety of circuit types. Through rigorous experimentation, qualitative and quantitative performance evaluations, we demonstrate effectiveness of GATE-Net and the supervised contrastive training of GATE-Net for HT detection.

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Section: Ht Trigger Detection With Gate-netmentioning

confidence: 99%

Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores

Muralidhar,

Zubair,

Weidler

et al. 2022

Preprint

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“…In [17], the structural features in gate-level netlist of both the HT circuits and the host circuits are examined and combined for HT detection. This method is based on the fact that the elusiveness of HTs relies on not just HT structure design but also on the insertion positions in the host circuits, in which HTs are usually inserted at either the low controllability position or the low observability position owning the stealth characteristic.…”

Section: Prior Work On Static Hardware Trojan Detectionmentioning

confidence: 99%

SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier

2021

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Security against Hardware Trojans (HT) is an important concern in integrated circuits (IC) design and fabrication. Most of the current HT detection methods are based on the golden model of circuit design. Further, some approaches require test pattern for HTs activation. In this paper, we propose SC-COTD (Sequential/Combinational Controllability and Observability features for hardware Trojan Detection), an effective hardware Trojan detection to get rid of both golden chip and test pattern limitations. SC-COTD uses both sequential and combinational testability measures to detect and locate HT signals by a machine learning approach. This method deploys an ensemble classifier based on k-means clustering. The clustering models have diverse variety in testability features along with size of clustering which inspect and reveal different aspects of netlist conventional for a collaborative scheme. The clustering results are filtered and then fed into a decision-making procedure based on majority voting to eliminate the limited flaws of each model. The evaluation results on TrustHUB benchmarks demonstrate that, SC-COTD can detect and locate HTs with 100% without any false negative, i.e., Recall = 1. Although our method has a limited number of false positive, it has the best performance in comparison to well-known previous approaches.

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“…Rajamanikkam et al [169] focused on an important threat in 3PIP: the architecture state preservation HT (TASP), and proposed three complementary techniques to detect the HT at a lower cost. Some are extremely novel methods: Liu et al [170] analyzed the combined structural characteristics of the HT and the main circuit and proposed a new HT detection technology. A feature database is constructed by extracting the structural characteristics of the combination logic and sequential logic in the group HT, and the author used the feature matching method to extract all of the features from the circuit structure.…”

Section: Specific Hts Protection Techniquesmentioning

confidence: 99%

Hardware Trojans in Chips: A Survey for Detection and Prevention

Dong

Liu

et al. 2020

Sensors

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Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

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A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits

Cited by 18 publications

References 27 publications

Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores

Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores

SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier

Hardware Trojans in Chips: A Survey for Detection and Prevention

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