FastCap: a multipole accelerated 3-D capacitance extraction program

Nabors, K.; White, Jacob K.

doi:10.1109/43.97624

Cited by 771 publications

(459 citation statements)

References 12 publications

(10 reference statements)

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“…For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.…”

Section: Interconnect Trends and Challengesmentioning

confidence: 77%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: Interconnect Trends and Challengesmentioning

confidence: 77%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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“…2 (a) 11.9474 1.96946 1.31162 Fig. 2 (b Figure (a) and (b) are about the same, we use another famous 3D field-solver FastCap [8] to extract the capacitances. The coupling capacitance C 12 is 1.745 fF in Figure (a) and 1.857 fF in Figure (b) for d g1 = 5µm.…”

Section: Ground-aware Net Routing Techniquesmentioning

confidence: 99%

Layout techniques for on-chip interconnect inductance reduction

Tu¹,

Jou²,

Chang³

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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-As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques − ground-aware net routing and source pin positioning − that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry [7] to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.

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“…Standard piecewise constant, higher order, or frequency-dependent basis functions have been used to represent J and ρ [18,16,19,20,21,22], and the basis function coefficients have been determined using both collocation and Galerkin methods applied to (1) and (2). There are also several choices for imposing the current and charge conservation conditions in (3) and (4) [16,23,24].…”

Section: Introductionmentioning

confidence: 99%

Automatic generation of geometrically parameterized reduced order models for integrated spiral RF-inductors

Daniel

White

Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation

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In this paper we describe an approach to generating low-order models of spiral inductors that accurately capture the dependence on both frequency and geometry (width and spacing) parameters. The approach is based on adapting a multiparameter Krylov-subspace based moment matching method to reducing an integral equation for the three dimensional electromagnetic behavior of the spiral inductor. The approach is demonstrated on a typical on-chip rectangular inductor.

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FastCap: a multipole accelerated 3-D capacitance extraction program

Cited by 771 publications

References 12 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

Layout techniques for on-chip interconnect inductance reduction

Automatic generation of geometrically parameterized reduced order models for integrated spiral RF-inductors

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