Fast secure processor for inhibiting software piracy and tampering

Yang, Jun; Zhang, Youtao; Lan, Guanghui

doi:10.1109/micro.2003.1253209

Cited by 25 publications

(4 citation statements)

References 16 publications

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“…In [51], the authors predict encryption counters for speculative OTP pre-computation. In [58,59], encryption counters are cached which can also further reduce our overheads.…”

Section: Secure Hardwarementioning

confidence: 99%

InvisiMem

Aga

Narayanasamy

2017

SIGARCH Comput. Archit. News

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A practically feasible low-overhead hardware design that provides strong defenses against memory bus side channel remains elusive. This paper observes that smart memory, memory with compute capability and a packetized interface, can dramatically simplify this problem. InvisiMem expands the trust base to include the logic layer in the smart memory to implement cryptographic primitives, which aid in addressing several memory bus side channel vulnerabilities efficiently. This allows the secure host processor to send encrypted addresses over the untrusted memory bus, and thereby eliminates the need for expensive address obfuscation techniques based on Oblivious RAM (ORAM). In addition, smart memory enables efficient solutions for ensuring freshness without using expensive Merkle trees, and mitigates memory bus timing channel using constant heartbeat packets. We demonstrate that InvisiMem designs have one to two orders of magnitude of lower overheads for performance, space, energy, and memory bandwidth, compared to prior solutions. CCS CONCEPTS • Security and privacy → Hardware-based security protocols; • Hardware → 3D integrated circuits;

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“…In [51], the authors predict encryption counters for speculative OTP pre-computation. In [58,59], encryption counters are cached which can also further reduce our overheads.…”

Section: Secure Hardwarementioning

confidence: 99%

InvisiMem

Aga

Narayanasamy

2017

SIGARCH Comput. Archit. News

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“…In the article by Yang et al (2003), the researchers present a technique in which the cryptography computation is shifted off from the memory access critical path by using a different encryption scheme, namely "one-time pad" encryption, to produce the instructions and data cipher-text. However, overall performance in multi-task systems and context switching is not well addressed.…”

Section: Related Workmentioning

confidence: 99%

Design and Performance Evaluation of the SCAN Secure Processor

Bourbakis

Kannavara

2015

International Journal of Monitoring and Surveillance Technologies Research

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This paper presents the design, performance analysis, security evaluation and the extended instruction set architecture (ISA) of the SCAN secure processor (SCAN-SP). The SCAN-SP is security enhanced SparcV8 processor architecture with an extended ISA to interface with an off-chip FPGA co-processor to handle lossless image compression, encryption and information hiding based on SCAN methodology. Additionally, SCAN-SP offers a SCAN methodology based secure computing feature capable of executing an encrypted instruction stream. Thus the proposed secure processor architecture enables tamper resistant code execution along with cryptographic and general computing capabilities.

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“…Many Yang et al, 2003) emphasize on memory encryption and authentication by efficient hardware approaches in single-core systems. Our proposed scheme focuses on on-chip secret protection in multi-core processors.…”

Section: Related Workmentioning

confidence: 99%

“…Pure soft-ware solutions itself cannot counter all attacks, therefore, enforcing security in processor design has drawn more and more attention. Currently many proposed works focus on encryption and authentication of hardware memory in singlecore systems (Gassend, Suh, Clarke, Dijk, & Devadas, 2003;Lee, Kwan, McGregor, Dwoskin, & Wang, 2005;Shi, Lee, Ghosh, Lu, & Boldyreva, 2005; Yan, Rogers, Englender, Solihin, & Prvulovic, 2006; Yang, Zhang, & Gao, 2003). They usually assume the processor core as a safe and secure unit.…”

Section: Introductionmentioning

confidence: 99%

SecCMP

Yang

Peng

Ramadass

2008

International Journal of Information Security and Privacy

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Security has been considered as an important issue in processor design. Most of the existing designs of security handling assume the chip as a single secure unit. However, such assumption is vulnerable to exposure resulted from a central failure point. In this article, we propose a secure Chip-Multiprocessor architecture (SecCMP) to handle security related problems such as key protection and core authentication in multi-core systems. Matching the nature of multi-core systems, a distributed threshold secret sharing scheme is employed to protect critical secrets. A critical secret (e.g., encryption key) is divided into multiple shares and distributed among multiple cores instead of being kept a single copy in one core that is sensitive to exposure. The proposed SecCMP can not only enhance the security and fault-tolerance in secret protection but also support core authentication. SecCMP is designed to be an efficient and secure architecture for CMPs.

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Fast secure processor for inhibiting software piracy and tampering

Abstract: Abstract

Cited by 25 publications

References 16 publications

InvisiMem

InvisiMem

Design and Performance Evaluation of the SCAN Secure Processor

SecCMP

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