Fast RNS FPL-based Communications Receiver Design and Implementation

Ramírez, J.; García, Antonio; Meyer-Baese, Uwe; Lloris, A.

doi:10.1007/3-540-46117-5_50

Cited by 51 publications

(34 citation statements)

References 9 publications

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“…This technique fundamentally differs from the implementation proposed by [10] in two critical issues. Firstly, this technique addresses the problem of multi-standard decimation filtering.…”

Section: Introductionmentioning

confidence: 90%

“…Secondly, and more importantly, since the implementation is multi-rate, the subsequent filters operate at lower sampling rates. Thus it reduces power consumption compared to the single stage implementation given in [10]. Furthermore, in the proposed architecture as the front end is a sigma-delta ADC, the forward converter which takes around 10% area of traditional RNS filter, is eliminated by suitably selecting the moduli set.…”

Section: Introductionmentioning

confidence: 99%

“…Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA/cdma2000 in [9]. A fast RNS field programmable logic (FPL) based communication receiver design and implementation is presented in [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

Shahana

Jose

James

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

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“…This technique fundamentally differs from the implementation proposed by [10] in two critical issues. Firstly, this technique addresses the problem of multi-standard decimation filtering.…”

Section: Introductionmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

Shahana

Jose

James

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…This technique fundamentally differs from the implementation proposed by [12] in two critical issues. Firstly, this technique addresses the problem of multi-standard decimation filtering.…”

Section: Introductionmentioning

confidence: 90%

“…Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA/cdma2000 in [11]. A fast RNS field programmable logic (FPL) based communication receiver design and implementation is presented in [12].…”

Section: Introductionmentioning

confidence: 99%

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX

Shahana

Jose

James

et al. 2008

VTC Spring 2008 - IEEE Vehicular Technology Conference

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Abstract-The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.

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RNS processor using moduli sets of the form 2ⁿ±1

Prediger

Bairros

Seman

et al. 2023

Circuit Theory & Apps

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Summary In recent years, research on residue number systems (RNS) has targeted larger dynamic ranges to explore their inherent parallelism further. In this paper, we start from the traditional 3‐moduli set false{2n,2n−1,2n+1false}, with an equivalent 3 n‐bit dynamic range, and propose balanced horizontal extensions by using modulus of the form 2n,0.1em2n−1 and 2n+1 to scale the dynamic range and enhance the parallelism according to the requirements. A method to design the reverse conversion by using it is also presented. A case study of multiplier‐accumulator (MACs) in cascade for filtering applications has been analyzed to validate the RNS processor using the proposed moduli set and reverse conversion architecture. Experimental results show that the proposed approaches achieve a significant speedup compared with the state‐of‐the‐art cases for the same dynamic range purposes.

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Fast RNS FPL-based Communications Receiver Design and Implementation

Cited by 51 publications

References 9 publications

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX

RNS processor using moduli sets of the form 2ⁿ±1

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Fast RNS FPL-based Communications Receiver Design and Implementation

Cited by 51 publications

References 9 publications

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX

RNS processor using moduli sets of the form 2n±1

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Product

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RNS processor using moduli sets of the form 2ⁿ±1