Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

Mansuri, M.; Liu, D.; Yang, Chih-Kong Ken

doi:10.1109/jssc.2002.803048

Cited by 142 publications

(60 citation statements)

References 2 publications

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“…According to two logical inputs, the charge pump consists of two switched current sources that pump charge into the loop filter or out of the filter. The circuit has three states [8]. If QA=0, QB=0, then both switches are off and output voltage remains constant.…”

Section: B Charge Pumpmentioning

confidence: 99%

Optimization of VLSI Architecture for High Performance PLL

Baluprithviraj¹

2017

IJRASET

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PLL itself is a mixed signal circuit which has design challenge at high frequencies. The phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. In this paper, the faster locking of the PLL is mainly concentrated by properly choosing the circuit architecture and parameters. The optimization of the VCO circuit is carried out to get a better frequency precision. The work characterizes the layout design of Phased Lock Loop PLL with multiple outputs. Effort has been made to design and implement using low power sub threshold D flip flop. The design implemented in analog design tool from Microwind 3.1 where each sub block is designed at its low power design.

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Section: B Charge Pumpmentioning

confidence: 99%

Optimization of VLSI Architecture for High Performance PLL

Baluprithviraj¹

2017

IJRASET

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“…When one of the PFD input rises the corresponding output becomes high. A pass transistor DFF based PFD architecture as in [4] is used in this PLL design. The simulation waveforms of PFD when Fref leads Fin are shown in the Fig.2.…”

Section: A Phase Frequency Detectormentioning

confidence: 99%

“…Hence a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tunable frequency range. The PFD described in [4] has been considered for its fast acquisition capability. The result of extensive simulation is reported here.…”

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confidence: 99%

Analysis and design of 1 GHz PLL for fast phase and frequency acquisition

Rout

Panda

Acharya

et al. 2014

IJSISE

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Abstract-Phase locked loops find wide application in several modern applications mostly in advance communication and instrumentation systems. PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The PLL is designed in GPDK090 library of CMOS 90nm process to operate at a frequency of 1GHz with a lock time of 280.6ns. This PLL circuit is observed to consume a power of 11.9mW from a 1.8-V DC supply. Keywords-Phase frequency detector (PFD), loop filter, voltage controlled oscillator (VCO), phase-locked loops (PLLs). I.INTRODUCTIONThe most versatile application of the phase locked loops (PLL)[1] is for clock generation and clock recovery in microprocessor, networking, parallel and serial data communication, and frequency synthesizers. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a mixed signal PLL [1] which must operate in the GHz range with less lock time. The PLL performance depends upon its order. If 'n' is the order of loop filter than 'n+1' is the order PLL [2]. The stability of the whole PLL system depends on the order of the loop filter. The voltage controlled oscillator (VCO) is the heart of the PLL. The present work focuses on the redesign of a PLL system using the 90nm technology. Hence a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tunable frequency range. The PFD described in [4] has been considered for its fast acquisition capability. The result of extensive simulation is reported here. The remaining part of the paper is organized as follows. Section II describes the general architecture of a PLL system. In section III the design and synthesis environment has been outlined. The results of simulation study are discussed in section IV. Finally the finding of the study has been concluded in section V.

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“…As the CL-PFD given in Fig. 1(a) cause dead zone, blind zone, lower gain, glitches at the output and associated large lock time and high reference spur [1,2], NL-PFDs have been proposed as a popular alternative [3,4,5]. Even though NL-PFDs offers higher gain, complicated design, complex circuits, presence of dead zone, blind zone and glitches at the output, all of these raise serious design constraints [4,5].…”

Section: Introductionmentioning

confidence: 99%

Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur

Kuppalath

Kailath

2016

IEICE Electron. Express

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A simple nonlinear PFD circuit designed to achieve reduced reference spur and faster acquisition process for a PLL is proposed in this paper. The proposed nonlinear PFD is found to offer higher gain, eliminate glitches at the output and reduce both dead zone and reset delay when compared with the operation of conventional linear PFD (CL-PFD) and conventional NL-PFD (CNL-PFD). The PLL acquisition time got reduced by 50% and 11.69% while the reference spur 45% and 38.6% with respect to the CL-PFD and CNL-PFD respectively. Reference spur of −72.2 dBc, lock time of 1.548 µs, area of 0.2 mm 2 and power dissipation of 6.2 mW are obtained for the prototype PLL using Proposed NL-PFD designed with 180 nm CMOS process.

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Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

Cited by 142 publications

References 2 publications

Optimization of VLSI Architecture for High Performance PLL

Optimization of VLSI Architecture for High Performance PLL

Analysis and design of 1 GHz PLL for fast phase and frequency acquisition

Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur

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