Optimization of VLSI Architecture for High Performance PLL

Abstract

PLL itself is a mixed signal circuit which has design challenge at high frequencies. The phase locked loop is designed using VLSI technology, which in turn offers high speed performance at low power. In this paper, the faster locking of the PLL is mainly concentrated by properly choosing the circuit architecture and parameters. The optimization of the VCO circuit is carried out to get a better frequency precision. The work characterizes the layout design of Phased Lock Loop PLL with multiple outputs. Effort has been made to design and implement using low power sub threshold D flip flop. The design implemented in analog design tool from Microwind 3.1 where each sub block is designed at its low power design.