Fast flip-chip power grid analysis via locality and grid shells

Chiprout, Eli

doi:10.1109/iccad.2004.1382626

Cited by 110 publications

(95 citation statements)

References 6 publications

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“…The incremental auxiliary drops caused by a current source keeps on decreasing as we move away from it. This is related to the concept of grid locality, which states that the effect of a current source diminishes as we move away from it [7]. Practically, these drops become so small after a few hops away that there is no point in computing them.…”

Section: Computing Auxiliary Dropsmentioning

confidence: 99%

Efficient RC power grid verification using node elimination

Goyal

Najm

2011

2011 Design, Automation &Amp; Test in Europe

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To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order Reduction (MOR) techniques to reduce the size of power grids but their focus is more on simulation. In verification, we are concerned about the safety of nodes, including the ones which have been eliminated in the reduction process. This paper proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes which are retained. Furthermore, a criterion for the safety of nodes which are removed is established based on the safety of other nearby nodes and a user specified margin.

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Section: Computing Auxiliary Dropsmentioning

confidence: 99%

Efficient RC power grid verification using node elimination

Goyal

Najm

2011

2011 Design, Automation &Amp; Test in Europe

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“…Examples of perturbations to a power network include changes to the wire conductances (e.g., when the length or thickness of the wires change), power pad placement, or current loads. For a small perturbation the solution of the perturbed system is close to the initial solution, meaning that the change in the solution of most of the nodes of the network is insignificant [5].…”

Section: Introductionmentioning

confidence: 99%

Incremental power network analysis using backward random walks

Boghrati

Sapatnekar

2012

17th Asia and South Pacific Design Automation Conference

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Abstract-The process of power network analysis during VLSI chip design is inherently iterative. It is very common for the designer to make many small perturbations to an otherwise complete design, to enhance the design or fix design violations. Considering the size of the modern chips, updating the solution for the changed network can be a computationally intensive task. In this paper we propose an efficient and accurate incremental solver that utilizes the backward random walks to identify the region of influence of the perturbation. The solution of the network is updated for the significantly smaller region only. The proposed algorithm is capable of handling consecutive perturbations without any degradation. The experimental results show speedups of up to 13.7× as compared to a complete solution.

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“…Even in the case that PCA cost is not acceptable, a region that is modeled at a time is reduced with a sacrifice of accuracy. However, power-voltage variation has a property of locality [17], and the local region is smaller than a chip, and hence the accuracy loss is thought to be limited. On the other hand, the execution time of Box-Cox transformation for 2000 variables each of which has 2000 samples was 37.5 s. The complexity of Box-Cox transformation (O(mn)) is lower than that of PCA (O(n 3 )), and hence the cost of Box-Cox transformation is not dominant even when the number of variables increases.…”

Section: ) Gaussianizationmentioning

confidence: 99%

Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise

Enami

Ninomiya

Hashimoto

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Power supply noise is having increasingly more influence on timing, even though noise-aware timing analysis has not yet been fully established, because of several difficulties such as its dependence on input vectors and dynamic behavior. This paper proposes static timing analysis that takes power supply noise into consideration where the dependence of noise on input vectors and spatial and temporal correlations are handled statistically. We construct a statistical model of power supply voltage that dynamically varies with spatial and temporal correlation, and represent it as a set of uncorrelated variables. We demonstrate that power-voltage variations are highly correlated and adopting principal component analysis as an orthogonalization technique can effectively reduce the number of variables. Experiments confirmed the validity of our model and the accuracy of timing analysis. We also discuss the accuracy and CPU time in association with the reduced number of variables.

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Fast flip-chip power grid analysis via locality and grid shells

Cited by 110 publications

References 6 publications

Efficient RC power grid verification using node elimination

Efficient RC power grid verification using node elimination

Incremental power network analysis using backward random walks

Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise

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