Efficient RC power grid verification using node elimination

Abstract

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order Reduction (MOR) techniques to reduce the size of power grids but their focus is more on simulation. In verification, we are concerned about the safety of nodes, including the ones which have been eliminated in the reduction process. This paper proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes which are retained. Furthermore, a criterion for the safety of nodes which are removed is established based on the safety of other nearby nodes and a user specified margin.

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip

“…Multigrid-like [24], [25], hierarchical [26], [27], partition-based [28] and Krylov subspace-based methods [29] are examples of MOR. Other works focused on reducing simulation time, for instance random walkbased simulation [30].…”

“…Power grids designed for real VLSI circuits may contain tens of thousands or even millions of nodes [43] which results in impractical simulation time and memory requirements. Thus, a coarse grid approach was used in many previous works [24], [25], [44]. In these works a multi-grid based model order reduction is used and the number of nodes in the power grid is reduced by node elimination.…”

High-Performance Spectral Methods for Computer-Aided Design of Integrated Circuits

“…In this case, It requires the underlying workloads or power densities to be known in advance [38,60,88], which may not always be practical. [15,25,26,33,34,50,70,81,105]. Recent research has made significant progress in reducing the power grid verification costs by using novel sparse approximate inverse (SPAI) technique [33], e cient dual algorithm [105], and node elimination [34].…”

“…[15,25,26,33,34,50,70,81,105]. Recent research has made significant progress in reducing the power grid verification costs by using novel sparse approximate inverse (SPAI) technique [33], e cient dual algorithm [105], and node elimination [34]. Despite these significant improvements, the overall power grid verification cost is still extremely high, especially for large-scale verification tasks.…”