Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method

Cook, Chase; Sun, Zeyu; Demircan, Ertugrul; Shroff, Mehul D.; Tan, Sheldon X.-D.

doi:10.1109/tvlsi.2018.2800707

Cited by 40 publications

(7 citation statements)

References 23 publications

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“…However, such method still primarily considers the EM stress without considering impacts from wire resistance changes of power grid networks. Cook et al proposed a nite difference analysis method, which was accelerated by Krylov subspace based reduction technique [12]. This method can be applied to general multi-segment interconnect wires with time-varying current and temperature.…”

Section: Em-induced Ir Analysis and Xing Workmentioning

confidence: 99%

“…Thirdly, it is to solve the stress and IR drop of interconnect wires in a coupled way. The coupled solver consists of a nite di erence time domain (FDTD) solver for EM stress [10,12] and a linear network DC IR drop solver. Lastly, all information will then feed into the EM check framework graphical user interface (GUI) for interactive user analysis.…”

Section: Preliminaries For Full-chip Em-induced Ir Drop Analysismentioning

confidence: 99%

“…In the past few years, research e orts focusing on so-called physicsbased EM analysis tool for power grid network analysis method have been explored [9,10,12,27]. However, all those methods need to solve the partial di erential equations (PDE) of hydrostatic stress in the multi-segment interconnect wires.…”

Section: Introductionmentioning

confidence: 99%

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GridNet

Zhou

Jin

Tan

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Em-induced Ir Analysis and Xing Workmentioning

confidence: 99%

Section: Preliminaries For Full-chip Em-induced Ir Drop Analysismentioning

confidence: 99%

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GridNet

Zhou

Jin

Tan

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…Furthermore, all existing power supply optimization methods fail to consider the aging effects. With recent advancements in physics-based EM models and numerical analysis techniques such as three-phase EM model [12,24,28,33], it is possible to provide more accurate time to failure (TTF) estimation for multi-segment interconnects.…”

Section: Introductionmentioning

confidence: 99%

EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks

et al. 2020

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This chapter provides techniques for power grid network sizing while considering electromigration reliability. Starting with power grid network and electromigration (EM) fundamentals. Specifically the concerns here are EM immortality and aging effects used as EM constraints when formulating the optimization problems. The chapter first shows that the new power/ground (P/G) optimization problem, subject to the voltage IR drop and new EM constraints, can still be formulated as an efficient sequence of linear programming (SLP) problem, where the optimization is carried out in two linear programming phases in each iteration. The new optimization will ensure that none of the wires fails if all the constraints are satisfied. However, requiring all the wires to be EM immortal can be over-constrained. To mitigate this problem, the improvement is to consider the aging effects of interconnect wires in P/G networks. The idea is to allow some short-lifetime wires to fail and optimize the rest of the wires while considering the additional resistance caused by the failed wire segments. In this way, the resulting P/G networks can be optimized such that the target lifetime of the whole P/G networks can be ensured and will become more robust and aging-aware over the expected lifetime of the chip.

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“…Recently, a number of physics-based EM models and assessment techniques have been proposed [1,[11][12][13][14][15][16][17][18][19][20][21][22]. Huang et al proposed a compact EM time-to-failure (TTF) model based on the approximate closed form solution of Korhonen's equation for a single wire and studied the impact that wire redundancy has on EM failure in the power grid networks [12,15,23]. This work has been extended to multi-segment wires [14] and timevarying current cases [18,19].…”

mentioning

confidence: 99%

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

Sadiqbatcha

Sun

Tan

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions iv at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours (about 10 5 X acceleration) under the 150 • C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs. v Contents List of Figures vii List of Tables viii List of Tables 3.1 TTF acceleration with various sink and main-branch configurations. .. .. 3.2 TTF acceleration with various sink, main segment, and reservoir configurations 4.1 Results from temperature based accelerated technique on the structure shown in Fig.

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Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method

Cited by 40 publications

References 23 publications

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EM Lifetime Constrained Optimization for Multi-Segment Power Grid Networks

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

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