Fast context switches: compiler and architectural support for preemptive scheduling

Snyder, Jeffrey S.; Whalley, David; Baker, Theodore P.

doi:10.1016/0141-9331(95)93086-x

Cited by 28 publications

(13 citation statements)

References 6 publications

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“…Others have developed techniques to reduce context switch overheads but have failed to synergistically exploit the property of idempotence. Snyder et al describe a compiler technique where each instruction is accompanied by a bit that indicates whether that instruction is a "fast context switch point" [37]. Zhou and Petrov also demonstrate how to pick low-overhead context switch points where there are few live registers [43].…”

Section: Related Workmentioning

confidence: 99%

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iGPU: Exception support and speculative execution on GPUs

Menon

Kruijf

Sankaralingam

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Since the introduction of fully programmable vertex shader hardware, GPU computing has made tremendous advances. Exception support and speculative execution are the next steps to expand the scope and improve the usability of GPUs. However, traditional mechanisms to support exceptions and speculative execution are highly intrusive to GPU hardware design. This paper builds on two related insights to provide a unified lightweight mechanism for supporting exceptions and speculation on GPUs.First, we observe that GPU programs can be broken into code regions that contain little or no live register state at their entry point. We then also recognize that it is simple to generate these regions in such a way that they are idempotent, allowing their entry points to function as program recovery points and enabling support for exception handling, fast context switches, and speculation, all with very low overhead. We call the architecture of GPUs executing these idempotent regions the iGPU architecture. The hardware extensions required are minimal and the construction of idempotent code regions is fully transparent under the typical dynamic compilation framework of GPUs. We demonstrate how iGPU exception support enables virtual memory paging with very low overhead (1% to 4%), and how speculation support enables circuit-speculation techniques that can provide over 25% reduction in energy.

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Section: Related Workmentioning

confidence: 99%

“…Restart markers [18] Loop analysis; not generalizable Idempotent processors [9] No liveness or SIMD analysis Fast switch points [37,43] [14] H/W and performance overheads State snapshotting [28] Exposes microarchitecture details Table 3: Prior work on exception and speculation recovery.…”

Section: Approach Weaknessmentioning

confidence: 99%

iGPU: Exception support and speculative execution on GPUs

Menon

Kruijf

Sankaralingam

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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“…4) Specific hardware services: Integrating new hardware services in a platform to improve the system predictability and reduce overheads is also possible [8]- [11]. These services show good results at reducing overheads and are often added at the processor level.…”

Section: Related Workmentioning

confidence: 99%

“…This approach however, usually entails a large degree of pessimism [4], [5] and a task set which is actually schedulable may end up being deemed unschedulable by the modified schedulability test [7]. The second approach consists in either using properties of the architecture or integrating new hardware services in the platform to improve the system predictability and reduce overheads [8]- [11], usually these services require processor modifications. Finally, designing a specific architecture with high predictability and specific design flow is also an option [12].…”

Section: Introductionmentioning

confidence: 99%

A context aware cache controller to bridge the gap between theory and practice in real-time systems

Allard

Nelissen

Goossens

et al. 2014

2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications

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Abstract-Nowadays, most processing platforms make use of cache memories to improve the execution speed of the tasks running on the processors. However, when a processor switches from a task to another, the caches must be reloaded with the context of the upcoming task. This is time consuming and is usually not predictable and thus affects the worst-case execution time of the task. Such unpredictability should be avoided in realtime systems in which the instant at which a result is available is as important as the result itself.In this paper, we present a hardware component named hardware context switch (HwCS) which replaces the standard L1 cache controller a processor. It divides the cache in two interchangeable layers and enables to save or restore the content of one layer while the second is simultaneously used as a usual cache by the processor. Saving the cache content after a preemption and restoring this content before resuming the execution of the preempted task, makes the preemption overheads negligible in comparison to the task worst-case execution times. It is theoretically proven that the existing scheduling theory can be used "as is" with the HwCS by simply reducing the task deadlines, thereby bridging the gap between theory and practice. The HwCS has been implemented in an uniprocessor system as a proof of concept. The first results show a neat improvements on the processor utilisation for a small cost in silicon surface.

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“…Several interrupts handling schemes to reduce the size of contexts to be switched to minimize the interrupt latency for VLIW and DSP processors are presented in [15][9] [22]. All these mechanisms need the support of a relative compiler and even processor architecture.…”

Section: Related Workmentioning

confidence: 99%

A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor

Anjam

Kong

Seedorf

et al. 2012

Lecture Notes in Computer Science

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Abstract. In this paper, we present a run-time task migration scheme for an adjustable/reconfigurable issue-slots very long instruction word (VLIW) multi-core processor. The processor has four 2-issue ρ-VEX VLIW cores that can be merged together to form larger issue-width cores. With a task migration scheme, a code running on a core can be shifted to a larger or a smaller issue-width core for increasing the performance or reducing the power consumption of the whole system, respectively. All the cores can be utilized in an efficient manner, as a core needed for a specific job can be freed at run-time by shifting its running code to another core. The task migration scheme is realized with the implementation of interrupts on the ρ-VEX cores. The design is implemented in a Xilinx Virtex-6 FPGA. With different benchmarks, we demonstrate that migrating a task running on a smaller issue-width core to a larger issuewidth core at run-time results in a considerable performance gain (up to 3.6x). Similarly, gating off one, two, three, or four cores can reduce the dynamic power consumption of the whole system by 24%, 42%, 61%, or 81%, respectively.

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Fast context switches: compiler and architectural support for preemptive scheduling

Cited by 28 publications

References 6 publications

iGPU: Exception support and speculative execution on GPUs

iGPU: Exception support and speculative execution on GPUs

A context aware cache controller to bridge the gap between theory and practice in real-time systems

A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor

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