Fast compensative design approach for the approximate squaring function

Sheu, Ming‐Hwa; Lin, Su-Hon

doi:10.1109/4.974551

Cited by 26 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is because FPGA tools can efficiently synthesize and map an adder in minimum LUT logic elements. [3] present two designs with "15" and "22" four-input LUT requirements (for 8-bit), respectively, and claim these to be better than the design proposed by Ming-Hwa and Su-Hon [4] which achieves 77% savings compared to a fullprecision squarer. Approximate squarers from Risojevic [5] and Cho et al [6] achieve 76% and 20% savings, respectively.…”

Section: Fpga Implementation Of Approximate Squarersmentioning

confidence: 95%

FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

Bilal

Masud

Athar

2012

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

This brief introduces a low-cost hardware design for approximate squaring functions which preserve maximum information content of the signals in template-matching applications. Analysis of signal statistics for two example applications, i.e., motion estimation and disparity estimation, is presented. This information is then specifically incorporated in the hardware design process to develop approximate squarers which outperform existing designs in hardware resource savings and performance while processing real-world data. Specifically, the proposed architectures make distinction between low-and high-entropy portions of the input data to intelligently trade off bit precision with hardware complexity. Mathematical and experimental results show mean-relative-error figures to be as low as 1.2% and the performance to be as good as conventional full-precision processing scenarios. Implementation results for current-generation six-input look up table (LUT) and four-input LUT FPGAs have been discussed in relation to the proposed design flow.Index Terms-Approximate processing, approximate squarer, error metric, FPGA implementation, sum of squared error (SSE).

show abstract

Section: Fpga Implementation Of Approximate Squarersmentioning

confidence: 95%

FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

Bilal

Masud

Athar

2012

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

show abstract

“…For this reason, many attempts have been made to achieve efficient implementations. One of such approaches is to develop approximate squarers [1][2][3]. The main drawback of this technique is the inaccuracy of the results, which cannot be tolerated in some applications such as in cryptography.…”

Section: Introductionmentioning

confidence: 98%

FPGA-Based Efficient Design Approaches for Large Size Two’s Complement Squarers

Gao

Chabini

Al-Khalili

et al. 2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

This paper presents two optimized design approaches of two's complement large size squarers using embedded multipliers in FPGAs. The realization of one of the approaches is based on Baugh-Wooley's algorithm and the other one is a new sign-extension technique. To achieve efficient implementation, a set of optimized schemes for the realization of multi-level additions of the partial products is proposed. The squarers are implemented for operands of sizes ranging from 20 to 128 bits targeting Xilinx' Spartan-3 using the ISE 8.1 synthesis and implementation tool, and from 38 to 128 bits targeting Altera's Stratix II using the Quartus II 6.0 synthesis and implementation tool. The comparisons indicate that our proposed approaches offer substantial area savings and delay reduction. Using the Baugh-Wooley-based approach, the average saving in LUTs is close to 50% with an average delay reduction in the range of 13% to 20%. With the new sign extension approach, the area saving ranges from 54% to 70%, while the delay is reduced by approximately 25%. Embedded block usage for both approaches with different tools is reduced by 38% compared with the standard schemes.

show abstract

“…Applications such as DSP, image processing and multimedia require extensive use of multiplication and squaring functions (Sheu and Lin, 2002;Walters et al, 2003). A full width digital n×n multiplier computes the 2n output as a weighted sum of partial products (Baugh and Wooley, 1973).…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Rais¹

2010

American Journal of Engineering and Applied Sciences

View full text Add to dashboard Cite

Problem statement: The development cost for Application Specific Integrated Circuits (ASICs) are high, algorithms should be verified and optimized before implementation. The Digital Signal Processing (DSP), image processing and multimedia requires extensive use of multiplication. The truncated multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. Approach: This research presented the comparative study of Spartan-3AN, Virtex-4 and Virtex-5 FPGA devices. The implementation of standard and truncated multipliers is done using Very high speed integrated circuit Hardware Description Language (VHDL). Results: Remarkable reduction in FPGA resources, delay and power was achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The three devices showed significant improvement for truncated multipliers as compared to standard multipliers. Results showed that the anomaly in Spartan-3AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 and Virtex-5 devices. Conclusion: The Virtex-5 FPGA device showed better performance as compared to Spartan-3AN and Virtex-4 FPGA devices

show abstract

Fast compensative design approach for the approximate squaring function

Cited by 26 publications

References 5 publications

FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

FPGA Design for Statistics-Inspired Approximate Sum-of-Squared-Error Computation in Multimedia Applications

FPGA-Based Efficient Design Approaches for Large Size Two’s Complement Squarers

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Contact Info

Product

Resources

About