Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields

Alrimeih, Hamad; Rakhmatov, Daler

doi:10.1109/tvlsi.2013.2294649

Cited by 57 publications

(43 citation statements)

References 26 publications

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“…Reference [29] illustrates how our multiplier's pipeline features can be utilized within a larger architecture of a programmable hardware processor for accelerating ECC point operations over NIST prime fields. The said processor can execute programmable sequences of computationally uniform blocks in an atomic fashion (to enhance security).…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Each atomic block consists of two modular multiplications, four modular additions/subtractions, five input data reads, and three data writes, all of which are integrated within a single pipeline (to enhance performance). The processor's 100-MHz Virtex-6 FPGA implementation reported in [29] takes between 0.30 ms (192-bit ECC) and 3.91 ms (521-bit ECC) to perform a typical scalar multiplication.…”

Section: Implementation Resultsmentioning

confidence: 99%

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Pipelined modular multiplier supporting multiple standard prime fields

Alrimeih

Rakhmatov

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Computationally-intensive cryptographic applications are critically dependent on the efficiency of modular multiplications. It is desirable for a modular multiplier to offer not only high performance, but also a certain degree of flexibility, supporting multiplications over finite fields of varying size. We propose a fast and flexible modular multiplier over five prime fields GF (p), standardized by NIST for use in elliptic curve cryptography, where the five special primes p are of size 192, 224, 256, 384, and 521 bits. A prime-specific datapath configuration of our multiplier is established automatically, based on an external control word that identifies a NIST prime in use. The pipeline latency of our multiplier (implemented on a Virtex-6 FPGA and running at 100 MHz) is 80 ns for 192-bit, 224-bit, and 256-bit NIST primes, and 200 ns for 384-bit and 521-bit NIST primes. The main limitation of this work is that our multiplier currently supports only the NIST prime fields. We believe that such a limitation is justifiable, as the NIST prime fields are widely used in practice and enable performance improvements through specialized hardware optimizations.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

Pipelined modular multiplier supporting multiple standard prime fields

Alrimeih

Rakhmatov

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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show abstract

“…Other works [1,20,36,19,29,27] outperform our architecture in terms of speed, but use a much larger number of embedded multipliers. Also, implementations only focusing on NIST curves are able to use the special prime shape, yielding a significant speed-up.…”

Section: Comparisonmentioning

confidence: 97%

Implementing Complete Formulas on Weierstrass Curves in Hardware

Massolino¹,

Renes²,

Batina³

2016

Security, Privacy, and Applied Cryptography Engineering

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Abstract. This work revisits the recent complete addition formulas for prime order elliptic curves of Renes, Costello and Batina in light of parallelization. We introduce the first hardware implementation of the new formulas on an FPGA based on three arithmetic units performing Montgomery multiplication. Our results are competitive with current literature and show the potential of the new complete formulas in hardware design. Furthermore, we present algorithms to compute the formulas using anywhere between two and six processors, using the minimum number of parallel field multiplications.

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“…In addition to key size, the Rijndael encryption algorithm also supports configuring the number of rounds, for which we consider a minimum of 10 rounds and a maximum of 14. In this paper, we consider ECC over binary fields due to the efficient hardware implementation thereof [31,32], but note that our approach can support other ECC implementations (e.g., ECC over prime fields [33]). …”

Section: Mixed Cryptography Security Modelmentioning

confidence: 99%

Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems

Nam

Lysecky

2018

Computers

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Abstract:Embedded systems continue to execute computational-and memory-intensive applications with vast data sets, dynamic workloads, and dynamic execution characteristics. Adaptive distributed and heterogeneous embedded systems are increasingly critical in supporting dynamic execution requirements. With pervasive network access within these systems, security is a critical design concern that must be considered and optimized within such dynamically adaptive systems. This paper presents a modeling and optimization framework for distributed, heterogeneous embedded systems. A dataflow-based modeling framework for adaptive streaming applications integrates models for computational latency, mixed cryptographic implementations for inter-task and intra-task communication, security levels, communication latency, and power consumption. For the security model, we present a level-based modeling of cryptographic algorithms using mixed cryptographic implementations. This level-based security model enables the development of an efficient, multi-objective genetic optimization algorithm to optimize security and energy consumption subject to current application requirements and security policy constraints. The presented methodology is evaluated using a video-based object detection and tracking application and several synthetic benchmarks representing various application types and dynamic execution characteristics. Experimental results demonstrate the benefits of a mixed cryptographic algorithm security model compared to using a single, fixed cryptographic algorithm. Results also highlight how security policy constraints can yield increased security strength and cryptographic diversity for the same energy constraint.

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Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields

Cited by 57 publications

References 26 publications

Pipelined modular multiplier supporting multiple standard prime fields

Pipelined modular multiplier supporting multiple standard prime fields

Implementing Complete Formulas on Weierstrass Curves in Hardware

Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems

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