Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers

Yuce, Bilgiday; Uğurdağ, H. Fatih; Gören, Sezer; Dündar, Günhan

doi:10.1109/tc.2014.2315634

Cited by 20 publications

(16 citation statements)

References 18 publications

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“…A literature survey is provided in [15], with circuits characterized as array-based or tree-based, depending on their logical design. The former ones are simpler, with bitwise comparisons of all candidates done in parallel, while the latter are more efficient in terms of latency.…”

Section: Related Workmentioning

confidence: 99%

“…BCT proposed in this paper is based on the optimized version of the Array Topology (AT) [15,22], namely, AT is based on a filtering approach where all candidates are processed in parallel from the most to the least significant bit (MSB to LSB). Progressively, the number of candidates in the calculation of the maximum element is reduced by using the enable signal.…”

Section: Array Topology (At)mentioning

confidence: 99%

“…The concise way of presenting the results is inspired by [15]. The area comparison of BCT with the reference circuits is given in Tables I and II.…”

Section: A Areamentioning

confidence: 99%

“…In the theoretical calculation based on BCT and AT logical designs, BCT consists of the same number of logic gates as AT in the lowest level of SB comparators. Namely, when calculating number of gates from the digital logic scheme, an 8-bit maximum selector in a set of 8 input elements based on AT consists of: That is in total 192 2-input gates and 8 8-input OR gates [23], where m-input logic gates can be implemented as a binary tree of m-1-unit gates [15]. This is in total 8*(8-1) = 56 gates for AT.…”

Section: A Areamentioning

confidence: 99%

“…This means that lower-level AT-cell in the same column cannot begin its work before the enable signal for that AT-cell is calculated in former AT-cell. Also, enable cannot be calculated before the winner data bit is generated, and all the winner bits cannot be calculated until all enable bits settle down [15]. Since in AT circuit next bit enable signal cannot be calculated before calculating the bit of the current maximum, this will cause one additional gate delay before calculating the winner bit.…”

Section: B Propagation Delaymentioning

confidence: 99%

See 4 more Smart Citations

Best-Choice Topology: An Optimized Array-based Maximum Finder

Prvan¹,

Ožegović²,

Soco³

et al. 2019

IJACSA

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Extracting maximum from an unsorted set of binary elements is important in many signal processing applications. Since quite few maximum-finder implementations are found in the recent literature, in this paper we provide an update on the current topic. Generally, maximum-finders are considered array-based, with parallel bit-by-bit comparison of the elements, or more efficient tree-based structures, with the hierarchical maximum extraction. In this paper, we concentrate on array-based topologies only, since our goal is to propose a new maximum-finder design called Best-Choice Topology (BCT), which is an optimized version of the standard Array Topology (AT). The usual bit-by-bit parallel comparison is applied for extracting the maximum and its one-of-N address. Boolean expressions are derived for BCT logical design and the minimum-finder equivalent. Functionality of the proposed architecture and the reference designs is verified with Xilinx ISE Design Suite 14.5. Synthesis is done on Application Specific Integrated Circuit (ASIC) TSMC 65nm technology. The conclusion of the paper is two-fold. First, we confirm the timing efficiency of BCT compared to AT. Next, we show that BCT is more efficient than the recent maximum-finder design called Maximum Magnitude Generator (MaxMG) and it has a great potential to be used for real-time signal processing applications.

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Section: Related Workmentioning

confidence: 99%

Section: Array Topology (At)mentioning

confidence: 99%

“…The concise way of presenting the results is inspired by [15]. The area comparison of BCT with the reference circuits is given in Tables I and II.…”

Section: A Areamentioning

confidence: 99%

Section: A Areamentioning

confidence: 99%

Section: B Propagation Delaymentioning

confidence: 99%

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Best-Choice Topology: An Optimized Array-based Maximum Finder

Prvan¹,

Ožegović²,

Soco³

et al. 2019

IJACSA

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Design of a novel energy efficient topology for maximum magnitude generator

Kathirvel¹,

Jangre

Ko³

2016

IET Computers & Digital Techniques

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A novel combinational digital device for finding maximum magnitude among the 'n' input numbers is proposed. This maximum magnitude generator (MaxMG) generates maximum magnitude as an output by utilising the bit by bit approach from multiple input (multi-bit) values simultaneously. MaxMG generates output from most significant bit (MSB) to least significant bit (LSB) in parallel, which utilises a minimum number of gate counts among the multi-bit of multiple input values. The minimum magnitude generator is also derived by applying the dual function to the MaxMG. The proposed design is implemented using Synopsys 90 nm generic library and RTL is written using Verilog HDL. The performance of the proposed design is compared with a rank based Kth max selection algorithm, a parallel tree based maximum generator utilised comparator-multiplexer combination, an array-based maximum finder (AB) and improved quad tree (IQT). The bit by bit parallel processing at the inputsfrom MSB to LSB, and the simple architecture utilising a minimum number of gates, makes the proposed design more energy efficient when compared with the Kth max algorithm, the tree based maximum finder, the AB based maximum finder, and the IQT architecture.

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