Design of a novel energy efficient topology for maximum magnitude generator

Abstract

A novel combinational digital device for finding maximum magnitude among the 'n' input numbers is proposed. This maximum magnitude generator (MaxMG) generates maximum magnitude as an output by utilising the bit by bit approach from multiple input (multi-bit) values simultaneously. MaxMG generates output from most significant bit (MSB) to least significant bit (LSB) in parallel, which utilises a minimum number of gate counts among the multi-bit of multiple input values. The minimum magnitude generator is also derived by applying the dual function to the MaxMG. The proposed design is implemented using Synopsys 90 nm generic library and RTL is written using Verilog HDL. The performance of the proposed design is compared with a rank based Kth max selection algorithm, a parallel tree based maximum generator utilised comparator-multiplexer combination, an array-based maximum finder (AB) and improved quad tree (IQT). The bit by bit parallel processing at the inputsfrom MSB to LSB, and the simple architecture utilising a minimum number of gates, makes the proposed design more energy efficient when compared with the Kth max algorithm, the tree based maximum finder, the AB based maximum finder, and the IQT architecture.

Power efficient error correction coding for on‐chip interconnection links

“…These are important parameters of the figure of merit (FOM) which are used for measuring the efficacy of a logic system [47–49]. The energy, performance, and quality of any digital implementation depend on the above parameters [48]. The comparison of the design cost of the proposed method with the state‐of‐the‐art works is discussed in Table 13.…”

“…PDP is the product of power dissipation () and combinational path delay () [48] and is given as PDP is an FOM associated with the efficiency of the design and is estimated when both power and performance have to be improved. It is the parameter which is most important in digital design at both device and circuit levels which reflects the speed‐power trade‐off in digital designs.…”

Best-Choice Topology: An Optimized Array-based Maximum Finder

“…Recently, authors in [16] proposed an ABT-based architecture that is more efficient in timing but detrimental to area and power. On the other hand, an efficient maximumfinder topology called Maximum Magnitude Generator (MaxMG) is implemented in [17]. The design is combinational and array-based, so it works as a filter comparing all input data bits in parallel.…”

“…The average power consumption is almost the same for BCT and AT as expected. MaxMG is considered one of the most energy efficient topologies in [17] outperforming tree-based and ABT-based circuits. However, in our experiment, MaxMG is almost three times slower than AT and BCT.…”