Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Abstract

Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt, a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

“…In Figure 7, with the increase of UNBS length, circuit reliability shows a decreasing thread, while runtime shows a slightly increasing thread, although fluctuations are observed. As mentioned above, circuits that require long UNBSs to reach convergence in the calculation tend to be of large scale or complicated structure, which tends to be low‐reliability 16,36 . In addition, the number of fault injection points in circuits at RTL is also an important factor affecting circuit reliability.…”

“…As mentioned above, circuits that require long UNBSs to reach convergence in the calculation tend to be of large scale or complicated structure, which tends to be low-reliability. 16,36 In addition, the number of fault injection points in circuits at RTL is also an important factor affecting F I G U R E 6 Effect of the proposed approach on runtimes before and after using GPU-based parallel schemes. GPU, graphics processing unit.…”

“…[12][13][14][15] Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits. 16 In the last few years, their negative effect on memory has been kept under control by using protection mechanisms, such as error-correcting codes. Meanwhile, soft errors taking place in combinational circuits have been reported to have increased by several orders of magnitude as the feature size of Complementary Metal Oxide Semiconductor devices decreases in nanofabrication technology, 17,18 which makes the reliability of combinational circuits an essential concern.…”

“…To shorten the product development cycle and improve market competitiveness, analyzing and estimating the impact of soft errors on circuit reliability at an early stage of circuit design is a growing need 12–15 . Historically, soft errors have been tackled in the context of memory cells because of the large chip area devoted to caches and the higher vulnerability of SRAM cells in comparison with combinational logic circuits 16 . In the last few years, their negative effect on memory has been kept under control by using protection mechanisms, such as error‐correcting codes.…”

Multiscale, Multiphysics Modeling and Simulation of Single-Event Effects in Digital Electronics: From Particles to Systems

“…Historically, soft errors have first affected memory circuits because of the large area of the chips devoted to caches and the higher vulnerability of SRAM cells in comparison to combinational logic [16]. However, technology scaling, especially in the past decade, has increased the SER in logic circuits by several orders of magnitude, making it comparable to the SER of unprotected memory for modern technologies [129]. In what follows we briefly examine the modeling of the SER in both memory circuits and in combinational logic.…”