Fast and accurate defect classification for CMP process monitoring

Lin, Yong-Yi; Tsai, Fu-Shou; Hsu, Lewis; Hsu, Hsin-Kuo; Li, Chih-Yueh; Ke, Yu-Yuan; Huang, Chih‐Wei; Chen, Jun Ming; Chang, Shou-Yi; Lee, Tung-Ying; Chen, Ethan; Cheng, Chien‐Chung

doi:10.1109/asmc.2019.8791750

Cited by 5 publications

(8 citation statements)

References 13 publications

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“…Silicon carbide (SiC) wafer with no pattern is thin slices or sheet-like structures, and has been widely used in semiconductor devices, sensors, power modules, and other applications due to its numerous outstanding properties. Typical defects on the surface of SiC include particles, scratches, etc, which affect the processing quality of subsequent processes and ultimately affect the product yield [9,10]. Particles are typically caused by tiny particles and contaminants in the air that adhere to the wafer surface.…”

Section: Instructionmentioning

confidence: 99%

Full-flow surface defect identification method based on spot scanning scattering for unpatterned wafer

Qu,

Zhou,

et al. 2024

J. Inst.

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As the critical dimensions of semiconductor manufacturing processes gradually decrease, the requirements for production yield management become increasingly stringent. During the manufacturing process, there are many different types of defects, such as micron-sized particles, millimeter-sized scratches, etc. Multiple categories and different scales bring great challenges to the detection and identification of defects. This paper provides a full-flow surface defect identification method based on spot scanning scattering for unpatterned wafers. First, an adaptive threshold method with dynamic kernel windows is used to perform line-by-line scanning inspection of the wafer Mercator image. The 3σ decision strategy is used to avoid the impact of defects on background estimation and to improve detection sensitivity. After morphological processing, connected domain analysis is performed to obtain the defect mask, and feature information such as the shape, size, and distribution of the defect is extracted. Finally, the defect identification is performed by rules based binning, and the identified defects are converted into wafer polar coordinate image for display and analysis. In the experiments, the proposed method is used to identify micron-scale particles as well as large scratches on the millimeter scale for SiC wafers. Relative to the actual production rate requirement of 20 wafers per hour, the analysis time for a 6-inch wafer is 24.4 s, which can meet the requirement. Meanwhile, the test results illustrate the effectiveness of the method. The proposed method is recommended for early-stage defect detection and identification of unpatterned wafers.

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Section: Instructionmentioning

confidence: 99%

Full-flow surface defect identification method based on spot scanning scattering for unpatterned wafer

Qu,

Zhou,

et al. 2024

J. Inst.

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“…σ i and σ n are the standard deviations of the panoramic image and the noise, respectively. KLA-Tencor also proposed the multi-die auto-threshold (MDAT) detection algorithm and the inline defect organizer (IDO) filtering algorithm to enable high-efficiency and high-sensitivity in-line defect inspection [184,185]. The MDAT algorithm uses multiple die information to create a median image, which will be utilized as the threshold reference to reduce the process noise and improve the defect extraction [184].…”

Section: Traditional Defect Inspection Algorithmsmentioning

confidence: 99%

“…The MDAT algorithm uses multiple die information to create a median image, which will be utilized as the threshold reference to reduce the process noise and improve the defect extraction [184]. The IDO filtering algorithm takes advantage of several defect properties such as feature vectors to automatically organize and eliminate nuisance defects [185]. As sub-10 nm manufacturing is entering the mainstream [186,187], advanced lithography techniques such as multiple patterning and EUV lithography will be used in the fab.…”

Section: Traditional Defect Inspection Algorithmsmentioning

confidence: 99%

Optical wafer defect inspection at the 10 nm technology node and beyond

Zhu¹,

Liu²,

Xu³

et al. 2022

Int. J. Extrem. Manuf.

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The growing demand for electronic devices, smart devices, and the Internet of Things constitutes the primary driving force for marching down the path of decreased critical dimension and increased circuit intricacy of integrated circuits. However, as sub-10 nm high-volume manufacturing is becoming the mainstream, there is greater awareness that defects introduced by original equipment manufacturer components impact yield and manufacturing costs. The identification, positioning, and classification of these defects, including random particles and systematic defects, are becoming more and more challenging at the 10 nm node and beyond. Very recently, the combination of conventional optical defect inspection with emerging techniques such as nanophotonics, optical vortices, computational imaging, quantitative phase imaging, and deep learning is giving the field a new possibility. Hence, it is extremely necessary to make a thorough review for disclosing new perspectives and exciting trends, on the foundation of former great reviews in the field of defect inspection methods. In this article, we give a comprehensive review of the emerging topics in the past decade with a focus on three specific areas: (1) the defect detectability evaluation, (2) the diverse optical inspection systems, and (3) the post-processing algorithms. We hope, this work can be of importance to both new entrants in the field and people who are seeking to use it in interdisciplinary work.

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“…( 6) Chemical monitoring: 21) A method of detecting materials that are mixed in and discharged with the slurry when film materials change. (7) Defect monitoring: 23) A method of inspecting not only the film thickness but also all the so-called defects as in (3). First, use the standalone instrument.…”

Section: Evolution Of Monitoringmentioning

confidence: 99%

CMP legend: revolution and evolution

Tsujimura¹

2022

Jpn. J. Appl. Phys.

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Since the invention of the transistor in 1947, semiconductors have seen phenomenal development in accordance with Moore's Law1), which is based on Dennard's theory2) on scaling. More than 30 years have passed since the advent of CMP3), the "most amazing technology that has contributed most to Moore’s law” according to Dr. Moore. Beginning with the CMP life cycle, this paper looks back on the history of CMP development, recognizes the current situation, and overlooks the future of polishing, cleaning, and monitoring. The paper also introduces the evolution of CMP, a revolutionary technology that emerged in the 1980s, together with some trivia from that period, and further introduces some episodes that are already or will be handed down as legends. In preparation for the paradigm revolution of semiconductors that is expected to occur in 2030, CMP software, as well as hardware, needs to advance more dramatically than before.

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Fast and accurate defect classification for CMP process monitoring

Cited by 5 publications

References 13 publications

Full-flow surface defect identification method based on spot scanning scattering for unpatterned wafer

Full-flow surface defect identification method based on spot scanning scattering for unpatterned wafer

Optical wafer defect inspection at the 10 nm technology node and beyond

CMP legend: revolution and evolution

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