Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions

Yoon, Seung Wook; Tang, Patrick; Emigh, Roger; Lin, Yaojian; Marimuthu, Pandi C.; Pendse, R.

doi:10.1109/ectc.2013.6575830

Cited by 54 publications

(5 citation statements)

References 2 publications

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“…This packaging method allows the die to shrink to a minimum size independent of the required area for an array of solder balls at industry standard BGA ball pitches [4]. It also allows for novel multi-die structures, 2.5D structures and 3D structures [5]. The Fan-out process has been qualified to a 28nm process node with the same dielectrics and Cu plating as are used in the eWLCSP process described here [5].…”

Section: The Encapsulated Wlcsp Processmentioning

confidence: 98%

“…It also allows for novel multi-die structures, 2.5D structures and 3D structures [5]. The Fan-out process has been qualified to a 28nm process node with the same dielectrics and Cu plating as are used in the eWLCSP process described here [5]. The eWLCSP process data presented in this paper was generated with a 300mm round reconstituted panel [2].…”

Section: The Encapsulated Wlcsp Processmentioning

confidence: 99%

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Encapsulated wafer level package technology (eWLCS)

Strothmann¹,

Yoon

Lin

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper introduces a new encapsulated WLCSP product (eWLCS). The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages existing high volume manufacturing methods with exceptionally high process yields. In this process the silicon wafer is diced prior to the wafer level packaging process. The dice are then reconstituted into a new wafer form with adequate distance between the die to allow for a thin layer of protective coating to remain after final singulation. Standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to a conventional WLCSP product with the addition of the protective sidewall coating. This paper discusses the key attributes of the new package as well as the manufacturing process used to create it. Reliability data will be presented and compared to conventional WLCSP products and improvements in package durability will be discussed and compared to conventional WLCSP.

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Section: The Encapsulated Wlcsp Processmentioning

confidence: 98%

Section: The Encapsulated Wlcsp Processmentioning

confidence: 99%

Encapsulated wafer level package technology (eWLCS)

Strothmann¹,

Yoon

Lin

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…STATSchipPAC proposed [34,140] using the fan-out flip chip-eWLB to make the RDLs for the chips to perform mostly lateral communications as shown in Fig. 36.…”

Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…The result is a proven 2.5D solution that is superior to TSV in terms of overall cost effectiveness and process simplicity as shown in Figure 3. [2]…”

Section: Proven Cost-effective 25d Integrationmentioning

confidence: 99%

Leading Edge Packaging Now the Realm of the OSATS

2013

Advancing Microelectronics Magazine

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Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions

Cited by 54 publications

References 2 publications

Encapsulated wafer level package technology (eWLCS)

Encapsulated wafer level package technology (eWLCS)

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Leading Edge Packaging Now the Realm of the OSATS

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