Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Lau, John H.; Li, Ming; Li, Margie; Chen, Tony; Xu, Iris; Yong, Qing Xiang; Zhong, Cheng; Fan, Na; Kuah, Eric; Li, Zhang; Tan, K. H.; Cheung, Y.M.; Ng, Eric; Lo, Penny; Wu, Kai; Hao, Ji; Wee, Koh Sau; Jiang, Runqing; Cao, Xi; Beica, Rozalia; Lim, Sze Pei; Nc, Lee; Ko, Cheng-Ta; Yang, Henry; Chen, Y-H.; Tao, Mian; Lo, Jeffery C. C.; Lee, S. W. Ricky

doi:10.1109/ectc.2018.00356

Cited by 23 publications

(7 citation statements)

References 24 publications

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“…Electronics packaging plays an important role in the semiconductor industry. Currently, the mainstream electronic packaging structures include heterogeneous packaging, 3D packaging, system-in-packaging (SiP), fan-out (FO) packaging, and wafer-level packaging [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 ]. With the increasing complexity of packaging structures, manufacturing reliability test vehicles, and conducting ATCT experiments have become time-consuming and very expensive processes, the design-on-experiment (DoE) methodology for packaging design is becoming infeasible.…”

Section: Introductionmentioning

confidence: 99%

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

et al. 2021

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Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

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Section: Introductionmentioning

confidence: 99%

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

et al. 2021

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“…这也意味着 5 nm 技术节点的突破, 将会使得集成电路技术发展面临一系列的新技术挑战. 在 SoC 减少特征尺寸 (比例缩小) 已经越来越难, 而且成本很高 [31] . 半导体集成电路重要的发展趋势是新型微波、低功鲁加国等: 后摩尔时代, 从有源相控阵天线走向天线阵列微系统 [32] .…”

Section: 天线阵列微系统概念和内涵unclassified

From active phased array antenna to antenna array microsystem in post-Moore era

Wang

2020

Sci. Sin.-Inf.

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“…The solder ball size is 200 lm, and the ball pitch is 0.4 mm. Figure 6 shows a 300 mm reconstituted wafer carrier with 629 (10 mm Â 10 mm) packages [45][46][47]. Each package has 4 (one 5 mm Â 5 mm and three 3 mm Â 3 mm) chips and 4 (0402) capacitors.…”

Section: (C)mentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Cited by 23 publications

References 24 publications

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging

From active phased array antenna to antenna array microsystem in post-Moore era

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

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