Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

Knežević, Miroslav; Kobayashi, Kazuyuki; Ikegami, Jun; Matsuo, Shin’ichiro; Satoh, Akashi; Koçabas, Ünal; Fan, Junfeng; Katashita, Toshihiro; Sugawara, Takeshi; Sakiyama, Kazuo; Verbauwhede, Ingrid; Ohta, Kazuo; Homma, Naofumi; Aoki, Takafumi

doi:10.1109/tvlsi.2011.2128353

Cited by 38 publications

(22 citation statements)

References 11 publications

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“…Both architectures are optimized for high-speed implementations, and it is therefore difficult to make a comparison with our unified coprocessor. We report in Table IX the latest FPGA implementation results of the five SHA-3 finalists (see for instance [20], [21] for a survey of parallel architectures). We consider here the least favorable case for Grøstl, in which a single block is processed.…”

Section: Results and Comparisonsmentioning

confidence: 99%

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

Beuchat

Okamoto

et al. 2017

Journal of Parallel and Distributed Computing

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Abstract-This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security. Thanks to a careful organization of AES and Grøstl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Grøstl are at least as good as the ones of the other SHA-3 finalists, our results show that Grøstl is the best candidate for low-area cryptographic coprocessors.

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Section: Results and Comparisonsmentioning

confidence: 99%

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

Beuchat

Okamoto

et al. 2017

Journal of Parallel and Distributed Computing

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“…More comprehensive efforts became feasible only after NIST's announcement of 14 candidates qualified to the second round of the competition in July 2009. Since then, several comprehensive studies in SHA-3 ASIC implementations have been reported [6]- [13]. Guo et al [6] used a consistent and systematic approach to move the SHA-3 hardware benchmark process from the FPGA prototyping by Kobayashi et al [14] to ASIC implementations based 130nm CMOS standard cell technology.…”

Section: Related Workmentioning

confidence: 99%

“…Henzen et al [9] implemented several architectures in a 90nm CMOS standard cell technology, targeting high-and moderatespeed constraints separately, and presented a complete benchmark of post-layout results. Knezevic et al [13] provided ASIC synthesis results in a 90nm CMOS standard cell technology as a comparison with their primary FPGA prototyping results. In December 2010, five candidates were selected for the last round of SHA-3 competition.…”

Section: Related Workmentioning

confidence: 99%

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ASIC implementations of five SHA-3 finalists

Guo¹,

Srivastav²,

Huang³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Throughout the NIST SHA-3 competition, in relative order of importance, NIST considered the security, cost, and algorithm and implementation characteristics of a candidate [1]. Within the limited one-year security evaluation period for the five SHA-3 finalists, the cost and performance evaluation may put more weight in the selection of winner. This work contributes to the SHA-3 hardware evaluation by providing timely cost and performance results on the first SHA-3 ASIC in 0.13 μm IBM process using standard cell CMOS technology with measurements of all the five finalists using the latest Round 3 tweaks. This article describes the SHA-3 ASIC design from VLSI architecture implementation to the silicon realization.

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“…Also, for several reasons a message is typically hashed first. Then, the hashvalue, as a representative of the message, is signed in place of the original message [10][11].…”

Section: Introductionmentioning

confidence: 99%

Fault Attacks Resistant Architecture for KECCAK Hash Function

Kahri¹,

Mestiri²,

Bouallègue³

et al. 2017

ijacsa

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Abstract-The KECCAK cryptographic algorithms widely used in embedded circuits to ensure a high level of security to any systems which require hashing as the integrity checking and random number generation. One of the most efficient cryptanalysis techniques against KECCAK implementation is the fault injection attacks. Until now, only a few fault detection schemes for KECCAK have been presented. In this paper, in order to provide a high level of security against fault attacks, an efficient error detection scheme based on scrambling technique has been proposed. To evaluate the robust of the proposed detection scheme against faults attacks, we perform fault injection simulations and we show that the fault coverage is about 99,996%. We have described the proposed detection scheme and through the Field-Programmable Gate Array analysis, results show that the proposed scheme can be easily implemented with low complexity and can efficiently protect KECCAK against fault attacks. Moreover, the FieldProgrammable Gate Array implementation results show that the proposed KECCAK fault detection scheme realises a compromise between implementation cost and KECCAK robustness against fault attacks.

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Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

Cited by 38 publications

References 11 publications

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

ASIC implementations of five SHA-3 finalists

Fault Attacks Resistant Architecture for KECCAK Hash Function

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