FAIR: a hardware architecture for real-time 3-D image registration

Castro-Pareja, Carlos R.; Jagadeesh, J.M.; Shekhar, Raj

doi:10.1109/titb.2003.821370

Cited by 49 publications

(48 citation statements)

References 27 publications

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“…There are several techniques developed using parallel computing [17][18][19][20][21]for fastest Image Registration has been developed. Some of them are "A Parallel GPU Algorithm for Mutual Information based 3D Non rigid Image Registration" [22], "A Parallel Mutual Information Based Image Registration Algorithm for Applications in Remote Sensing" [23], "GPU Accelerated Medical Image Registration Techniques" [24], "Acceleration of Genetic Algorithm with Parallel Processing with Application in Medical Image Registration" [25], "Parallel Image Registration Using Bio-Inspired Computing" [26], "Multimodal Image Registration Using GPU Parallel Computing Technology" [27], "Fast Parallel Image Registration On CPU And GPU For Diagnostic Classification Of Alzheimer's Disease" [28], "Histogram-Based Image Registration Using Parallel Computing" [29].…”

Section: Mutual Informationmentioning

confidence: 99%

Multithreaded Approach for Registration of Medical Images using Mutual Information in Multicore Environment and its Applications in Medical Imaging

Saxena¹,

Sharma²,

Sharma³

2015

IJCA

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Image Registration plays very crucial role in case of medical imaging to register different modalities of images like CT (Computed Tomography) and PET (Positron Emission Tomography) registration. CT is essential for structural information of anatomic and PET (Positron Emission Tomography) is for functional information. Basically it is the procedure of transforming dissimilar sets of data into one coordinate system. These sets of data can be acquired from multiple image modalities, different viewpoints, similar or dissimilar sensors. MI based image registration has been found to be reasonably useful methods of image registration. However, it is found to be quite computationally intensive and time consuming process for enormous size images and for different data sets of images. It involves steps for computation of joint histogram, marginal entropies, calculation and probability distribution. Main motive of this paper is to provide an intelligent method for image registration based on Mutual Information using multi core environment with maintaining the synchronization between different activated cores and processors. Proposed Method has been able to execute with different number of threads to achieve all the remuneration of the processors and gives significant speedup working with verity of images like gray scale, RGB and Dicom images with different size. Finally the designed algorithm has been used to register medical images of different modalities.

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Section: Mutual Informationmentioning

confidence: 99%

Multithreaded Approach for Registration of Medical Images using Mutual Information in Multicore Environment and its Applications in Medical Imaging

Saxena¹,

Sharma²,

Sharma³

2015

IJCA

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“…Fast automatic image registration (FAIR) [4] is such an architecture proposed by Castro-Pareja et al for accelerated hardware implementation of rigid image registration. FAIR is optimized and fine tuned for partial-volumeinterpolation-based image registration by means of pipelining, parallel memory access, and distributed processing.…”

Section: Fpga Technologymentioning

confidence: 99%

“…Speedup of registration is achieved by identifying throughput bottle neck areas and optimizing them in order to decrease the processing time. Speedup of the algorithm can be obtained by using pipelined architectures and also by using parallel architectures [4]. Since the majority of the registration execution time is spent on calculating the mutual histogram, accelerating mutual histogram calculation has been the focus of our work.…”

Section: Computation Of Mutual Informationmentioning

confidence: 99%

Model-based mapping of reconfigurable image registration on FPGA platforms

Sen

Hemaraj

Plishker

et al. 2008

J Real-Time Image Proc

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Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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“…Memory organization and neighborhood access techniques are often the limiting factors in 3D image processing systems [139][140][141][142]. However, most practical filtering techniques employ standard neighborhood operations that require block- begins.…”

Section: Memory Controller and Brick-caching Schemementioning

confidence: 99%

“…Castro-Pareja et al [139] have shown that, for typical medical images, accumulating In general, the execution time T required by a pipelined implementation (with n-stages) of an operation is given as:…”

Section: Acceleration Approachmentioning

confidence: 99%

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Dandekar¹

2008

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Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissues, and lead to faster patient recovery. Advanced three-dimensional (3D) image processing is a critical need for navigation during IGIs. However, achieving on-demand performance, as required by IGIs, for these image processing operations using software-only implementations is challenging because of the sheer size of the 3D images, and memory and compute intensive nature of the operations. This dissertation, therefore, is geared toward developing high-performance 3D image processing architectures, which will enable improved intraprocedural visualization and navigation capabilities during IGIs.In this dissertation we present an architecture for real-time implementation of 3D filtering operations that are commonly employed for preprocessing of medical images. This architecture is approximately two orders of magnitude faster than corresponding software implementations and is capable of processing 3D medical images at their acquisition speeds. Report Documentation PageCombining complementary information through registration between pre-and intraprocedural images is a fundamental need in the IGI workflow. Intensity-based deformable registration, which is completely automatic and locally accurate, is a promising approach to achieve this alignment. These algorithms, however, are extremely compute intensive, which has prevented their clinical use. We present an FPGA-based architecture for accelerated implementation of intensity-based deformable image registration. This high-performance architecture achieves over an order of magnitude speedup when compared with a corresponding software implementation and reduces the execution time of deformable registration from hours to minutes while offering comparable image registration accuracy.Furthermore, we present a framework for multiobjective optimization of finite-precision implementations of signal processing algorithms that takes into account multiple conflicting objectives such as implementation accuracy and hardware resource consumption. The evaluation that we have performed in the context of FPGA-based image registration demonstrates that such an analysis can be used to enhance automated hardware design processes, and efficiently identify a system configuration that meets given design constraints. In addition, we also outline two novel clinical applications that can directly benefit from these developments and demonstrate the feasibility of our approach in the context of these applications. These advances will ultimately enable integration of 3D image processing into clinical workflow.

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FAIR: a hardware architecture for real-time 3-D image registration

Cited by 49 publications

References 27 publications

Multithreaded Approach for Registration of Medical Images using Mutual Information in Multicore Environment and its Applications in Medical Imaging

Multithreaded Approach for Registration of Medical Images using Mutual Information in Multicore Environment and its Applications in Medical Imaging

Model-based mapping of reconfigurable image registration on FPGA platforms

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

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